User contributions for Asie

22 August 2023

• 09:5809:58, 22 August 2023 diff hist +594‎ I/O port map ‎No edit summary
• 09:1509:15, 22 August 2023 diff hist +2,096‎ Display ‎No edit summary
• 09:1309:13, 22 August 2023 diff hist −1‎ I/O port map ‎No edit summary
• 08:2908:29, 22 August 2023 diff hist +174‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary current
• 08:2508:25, 22 August 2023 diff hist +2,011‎ Display ‎No edit summary
• 08:1608:16, 22 August 2023 diff hist +5,990‎ N Display ‎ initial page
• 06:4806:48, 22 August 2023 diff hist +10‎ Memory map ‎No edit summary
• 06:4706:47, 22 August 2023 diff hist +239‎ Memory map ‎No edit summary
• 06:4606:46, 22 August 2023 diff hist 0‎ m Memory map ‎No edit summary
• 06:4606:46, 22 August 2023 diff hist +12‎ m Memory map ‎No edit summary
• 06:4606:46, 22 August 2023 diff hist +40‎ Memory map ‎No edit summary
• 06:4506:45, 22 August 2023 diff hist +22‎ WSdev Wiki ‎ split console and cartridge components
• 06:4406:44, 22 August 2023 diff hist +3,313‎ N Memory map ‎ Created page with "The WonderSwan's SoC enforces the following memory map layout: {| class="wikitable" |+ WonderSwan SoC linear memory map ! Bus ! colspan="2" | Address range ! Access width ! Access speed ! Read/Write |- | Internal | colspan="2" style="text-align: center;" | 0x00000<br/>0x0FFFF | 16-bit | 1 cycle | RW |- | rowspan="2" | Cartridge | rowspan="2" style="text-align: center;" | 0x10000<br/>0xFFFFF | style="text-align: center;" | 0x10000<br/>0x1FFFF | 8-bit | ??? | RW |- | styl..."
• 06:2206:22, 22 August 2023 diff hist +33‎ Timers ‎No edit summary
• 05:5505:55, 22 August 2023 diff hist +154‎ Timing ‎No edit summary
• 05:5105:51, 22 August 2023 diff hist +123‎ I/O port map ‎ update timer information
• 05:5105:51, 22 August 2023 diff hist +1,409‎ N Timers ‎ Created page with "The WonderSwan features two timers: * Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles), * Vertical Blank Timer - counts down every frame. The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically. == Interrupts == Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer cond..."
• 05:4305:43, 22 August 2023 diff hist −1‎ m Interrupts ‎No edit summary
• 05:4005:40, 22 August 2023 diff hist +1,251‎ N UART ‎ Created page with "The WonderSwan's EXT port features an UART operating with the following configuration: * 9,600 or 38,400 bps (bauds per second), * 8N1 (8 data bits followed by 1 stop bit, no parity). This allows for an effective maximum transfer speed of ~1066 or ~4266 bytes per second, respectively. The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console. == Interrupts == The UART features tw..."
• 05:3905:39, 22 August 2023 diff hist +45‎ I/O port map ‎ update UART information
• 05:3305:33, 22 August 2023 diff hist +87‎ Interrupts ‎No edit summary
• 05:3205:32, 22 August 2023 diff hist +259‎ I/O port map ‎ update interrupt information
• 05:3105:31, 22 August 2023 diff hist +2,116‎ N Interrupts ‎ Created page with "The WonderSwan features fourteen different interrupts: * CPU interrupts - six provided by the V30MZ CPU ($00-$05), * Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset <code>V</code>): ** Level - will be reissued so long as the prerequisite condition is raised or the interrupt is disabled, ** Edge - will only be issued once; acknowledging the interrupt prevents reissuing until the conditi..."

21 August 2023

• 19:5319:53, 21 August 2023 diff hist −26‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5319:53, 21 August 2023 diff hist −1‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5319:53, 21 August 2023 diff hist +11‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5119:51, 21 August 2023 diff hist +22‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5119:51, 21 August 2023 diff hist +651‎ WonderGate/bplXX.mopera.ne.jp ‎ initial multipart block documentation
• 18:0018:00, 21 August 2023 diff hist +205‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary

20 August 2023

• 19:1019:10, 20 August 2023 diff hist +28‎ I/O port map ‎ consistency: add more URLs
• 19:1019:10, 20 August 2023 diff hist −7‎ WSdev Wiki ‎ consistency: rename Serial port to UART
• 19:0919:09, 20 August 2023 diff hist +82‎ I/O port map ‎ add cartridge I/o link

19 August 2023

• 18:1218:12, 19 August 2023 diff hist +96‎ WonderGate ‎No edit summary
• 18:0918:09, 19 August 2023 diff hist +161‎ WonderGate ‎No edit summary
• 18:0718:07, 19 August 2023 diff hist +295‎ N WonderWave ‎ Created page with "The WonderWave is an infrared adapter for the WonderSwan. It is implemented as a bi-directional 9600 bps converter between IrDA and the WonderSwan's UART <ref>[http://www.wonderwitch.com/neta/waza035/index.html 技その35「WonderWaveでファイル転送」]</ref>. == Notes == <references />" current
• 15:4715:47, 19 August 2023 diff hist +124‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:4415:44, 19 August 2023 diff hist +8‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:1515:15, 19 August 2023 diff hist +302‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:0415:04, 19 August 2023 diff hist +62‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 13:5713:57, 19 August 2023 diff hist −17‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 13:1113:11, 19 August 2023 diff hist +36‎ m Bandai 2003 ‎ make it clearer that RTC Command and Status are the same port, unify capitalization
• 12:0512:05, 19 August 2023 diff hist +128‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 11:1711:17, 19 August 2023 diff hist +1,467‎ N WonderGate/bplXX.mopera.ne.jp ‎ Created page with "For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests: * <code>bpl01.mopera.ne.jp</code> * <code>bpl02.mopera.ne.jp</code> == Packet format == Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers. The client expects one block in response from the server. === Header === {| class="wikitable" ! Offset ! Leng..."
• 11:0711:07, 19 August 2023 diff hist +201‎ N WonderGate ‎ Created page with "== WonderGate == TODO === Servers === {| class="wikitable" |+ WonderGate servers |- ! Hostname !! Software |- | bplXX.mopera.ne.jp || MobileWonderGate (browser) |}"

18 August 2023

• 08:4208:42, 18 August 2023 diff hist +474‎ ROM header ‎ add missing developer/publisher IDs (from up-n-atom)

17 August 2023

• 09:2909:29, 17 August 2023 diff hist +23‎ Keypad ‎No edit summary
• 09:2809:28, 17 August 2023 diff hist +2,746‎ N Keypad ‎ Created page with "The WonderSwan SoC features a 4 by 3 keypad matrix. == Scanning == Scanning is done via writing to and reading from port $B5. <pre> 7 bit 0 ---- ---- .iii oooo ||| ++++- Output rows (0-3) +++------ Input rows (4-6) </pre> The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so: <pre> 15 bit 0 ---- ---- ---- ---- .... 4444 5555 6666 </pre> Typical keypad scanning implementations introduce a d..."
• 09:1809:18, 17 August 2023 diff hist +128‎ I/O port map ‎ clarify keypad port

16 August 2023

• 22:3322:33, 16 August 2023 diff hist +40‎ m I/O port map ‎ Mono Shade LUT
• 22:3122:31, 16 August 2023 diff hist +17,163‎ N I/O port map ‎ Created page with "* Superscripts are used to mark ports specific to a given mode or platform: ** Color mode: ^(color). ** WS/WSC/SC console: ^(WS), ^(WSC), ^(SC). * If two Bits rows are provided, the second one refers to the "Color" mode. * The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word). {| class="wikitable" ! Category ! Port ! Description ! Bits ! Type ! Notes |- ! rowspan="45" | Displ..."