Bandai 2003
The Bandai 2003 (LUXSOR2) is one of the two mappers used in WonderSwan cartridges.
In addition to the normal Mapper banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.
Category | Port | Description | Bits | Type | Notes |
---|---|---|---|---|---|
RTC | $CA | RTC Command | ...1 CCCC | W8 | Command (C) |
RTC Status | R00B CCCC | R8 | Busy (B), Command (C), Ready (R) | ||
$CB | RTC Payload | dddd dddd | RW8 | Data (d) | |
GPO | $CC | GPO Data Direction | 0000 oooo | RW8 | 1 = output, 0 = high-impedance (weak pull-down) |
$CD | GPO Data | 0000 dddd | RW8 | 1 = 3V, if enabled by data direction | |
Self-Flash | $CE | Self-Flash Control | 0000 000r | RW8 | 1 = ROM is accessed via the 0x10000 - 0x1FFFF memory region.
0 = RAM is accessed via the region. |
Extended bankswitching | $CF | ROM Linear (EX) Bank | 00bb bbbb | RW8 | Selects a 1MiB bank accessed via memory addresses 0x40000 - 0xFFFFF.
Identical to the $C0 port. |
$D0 | RAM(/ROM) Bank | 0000 00bb bbbb bbbb | RW16 | Selects a 64KiB bank accessed via memory addresses 0x10000 - 0x1FFFF.
Lower 8 bits are identical to the $C1 port. | |
$D2 | ROM0 Bank | 0000 00bb bbbb bbbb | RW16 | Selects a 64KiB bank accessed via memory addresses 0x20000 - 0x2FFFF.
Lower 8 bits are identical to the $C2 port. | |
$D4 | ROM1 Bank | 0000 00bb bbbb bbbb | RW16 | Selects a 64KiB bank accessed via memory addresses 0x30000 - 0x3FFFF.
Lower 8 bits are identical to the $C3 port. |
Real-Time Clock
The 2003's RTC interface is a simple half-duplex SPI-like protocol.
For specifics of what the S-3511A expects to be done with these bytes, see Real-Time Clock.
Usage
Writing a valid command (see below) to port $CA will start a command transaction. The value of the command can be read from $CA; for valid commands, bit 4 will be cleared once the command is completed; for invalid commands, bit 4 will remain as written.
The Busy bit is set for the duration of a command transaction being processed, including when payload bytes are expected to be written or read.
The Ready bit is set when $CB is ready for access - both after each byte written or read, as well as at the end of a command (including zero-byte commands like $10). It is cleared when a payload byte is written (for commands which expect writes), read (for commands which expect reads), or either written or read (when the Busy bit is clear).
For commands which require bytes to be sent, the first byte should be written to port $CB before starting the command with a port $CA write. The 2003 will pause for subsequent bytes and set bit 7, if necessary.
For commands which return bytes to be read, they can be accessed through port $CB after the Ready bit is set or if the Busy bit is clear.
If there is no external S-3511A, all bytes will read back as $FF due to a weak pull-up inside the 2003.
Commands
Each valid command sends its command byte, followed by a fixed number of payload bytes to be sent or received.
Invalid commands immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.
Command | Command byte | Bytes to RTC | Bytes from RTC |
---|---|---|---|
$00 - $0F | N/A | ||
$10 | $60 | None | |
$11 | $61 | None | |
$12 | $62 | 1 | |
$13 | $63 | 1 | |
$14 | $64 | 7 | |
$15 | $65 | 7 | |
$16 | $66 | 3 | |
$17 | $67 | 3 | |
$18 | $68 | 2 | |
$19 | $69 | 2 | |
$1A | $6A | 2 | |
$1B | $6B | 2 | |
$1C - $1F | N/A |
Self-flashing
The 2003 mapper allows mapping the ROM chip in the PSRAM area using the $CE port. This can be used for writing to a NOR flash chip acting as the cartridge's ROM.
Note that the SRAM memory area is always accessed in byte as opposed to word mode. This means that, if the ROM/flash chip is normally accessed in word mode, the $CE port will only work correctly with the /BYTE pin connected to the mapper.
Lockout
Unlike the 2001 mapper, the 2003 mapper checks for the address line changes which are part of the authentication handshake after power-up. Until this handshake occurs, ROM access is inhibited. (TODO: How exactly?)