User contributions for Asie

22 August 2023

• 06:4406:44, 22 August 2023 diff hist +3,313‎ N Memory map ‎ Created page with "The WonderSwan's SoC enforces the following memory map layout: {| class="wikitable" |+ WonderSwan SoC linear memory map ! Bus ! colspan="2" | Address range ! Access width ! Access speed ! Read/Write |- | Internal | colspan="2" style="text-align: center;" | 0x00000<br/>0x0FFFF | 16-bit | 1 cycle | RW |- | rowspan="2" | Cartridge | rowspan="2" style="text-align: center;" | 0x10000<br/>0xFFFFF | style="text-align: center;" | 0x10000<br/>0x1FFFF | 8-bit | ??? | RW |- | styl..."
• 06:2206:22, 22 August 2023 diff hist +33‎ Timers ‎No edit summary
• 05:5505:55, 22 August 2023 diff hist +154‎ Timing ‎No edit summary
• 05:5105:51, 22 August 2023 diff hist +123‎ I/O port map ‎ update timer information
• 05:5105:51, 22 August 2023 diff hist +1,409‎ N Timers ‎ Created page with "The WonderSwan features two timers: * Horizontal Blank Timer - counts down every horizontal blank (256 CPU cycles), * Vertical Blank Timer - counts down every frame. The timers also feature an auto-reload functionality: that is, they can be configured to fire one time or repeat periodically. == Interrupts == Each timer has its own interrupt; it is triggered when the counter would be about to count down to zero, that is when the counter's value is 1 and the timer cond..."
• 05:4305:43, 22 August 2023 diff hist −1‎ m Interrupts ‎No edit summary
• 05:4005:40, 22 August 2023 diff hist +1,251‎ N UART ‎ Created page with "The WonderSwan's EXT port features an UART operating with the following configuration: * 9,600 or 38,400 bps (bauds per second), * 8N1 (8 data bits followed by 1 stop bit, no parity). This allows for an effective maximum transfer speed of ~1066 or ~4266 bytes per second, respectively. The hardware also features a one-byte transmit and receive buffer, which allows for a slight delay in code when handling data to/from the console. == Interrupts == The UART features tw..."
• 05:3905:39, 22 August 2023 diff hist +45‎ I/O port map ‎ update UART information
• 05:3305:33, 22 August 2023 diff hist +87‎ Interrupts ‎No edit summary
• 05:3205:32, 22 August 2023 diff hist +259‎ I/O port map ‎ update interrupt information
• 05:3105:31, 22 August 2023 diff hist +2,116‎ N Interrupts ‎ Created page with "The WonderSwan features fourteen different interrupts: * CPU interrupts - six provided by the V30MZ CPU ($00-$05), * Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset <code>V</code>): ** Level - will be reissued so long as the prerequisite condition is raised or the interrupt is disabled, ** Edge - will only be issued once; acknowledging the interrupt prevents reissuing until the conditi..."

21 August 2023

• 19:5319:53, 21 August 2023 diff hist −26‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5319:53, 21 August 2023 diff hist −1‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5319:53, 21 August 2023 diff hist +11‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5119:51, 21 August 2023 diff hist +22‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 19:5119:51, 21 August 2023 diff hist +651‎ WonderGate/bplXX.mopera.ne.jp ‎ initial multipart block documentation
• 18:0018:00, 21 August 2023 diff hist +205‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary

20 August 2023

• 19:1019:10, 20 August 2023 diff hist +28‎ I/O port map ‎ consistency: add more URLs
• 19:1019:10, 20 August 2023 diff hist −7‎ WSdev Wiki ‎ consistency: rename Serial port to UART
• 19:0919:09, 20 August 2023 diff hist +82‎ I/O port map ‎ add cartridge I/o link

19 August 2023

• 18:1218:12, 19 August 2023 diff hist +96‎ WonderGate ‎No edit summary
• 18:0918:09, 19 August 2023 diff hist +161‎ WonderGate ‎No edit summary
• 18:0718:07, 19 August 2023 diff hist +295‎ N WonderWave ‎ Created page with "The WonderWave is an infrared adapter for the WonderSwan. It is implemented as a bi-directional 9600 bps converter between IrDA and the WonderSwan's UART <ref>[http://www.wonderwitch.com/neta/waza035/index.html 技その35「WonderWaveでファイル転送」]</ref>. == Notes == <references />" current
• 15:4715:47, 19 August 2023 diff hist +124‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:4415:44, 19 August 2023 diff hist +8‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:1515:15, 19 August 2023 diff hist +302‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 15:0415:04, 19 August 2023 diff hist +62‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 13:5713:57, 19 August 2023 diff hist −17‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 13:1113:11, 19 August 2023 diff hist +36‎ m Bandai 2003 ‎ make it clearer that RTC Command and Status are the same port, unify capitalization
• 12:0512:05, 19 August 2023 diff hist +128‎ WonderGate/bplXX.mopera.ne.jp ‎No edit summary
• 11:1711:17, 19 August 2023 diff hist +1,467‎ N WonderGate/bplXX.mopera.ne.jp ‎ Created page with "For the MobileWonderGate software, NTT DoCoMo operated network servers for validating and redirecting URL requests: * <code>bpl01.mopera.ne.jp</code> * <code>bpl02.mopera.ne.jp</code> == Packet format == Every packet sent from and to the server follows the same format: a global header, followed by an arbitrary number of blocks with their respective headers. The client expects one block in response from the server. === Header === {| class="wikitable" ! Offset ! Leng..."
• 11:0711:07, 19 August 2023 diff hist +201‎ N WonderGate ‎ Created page with "== WonderGate == TODO === Servers === {| class="wikitable" |+ WonderGate servers |- ! Hostname !! Software |- | bplXX.mopera.ne.jp || MobileWonderGate (browser) |}"

18 August 2023

• 08:4208:42, 18 August 2023 diff hist +474‎ ROM header ‎ add missing developer/publisher IDs (from up-n-atom)

17 August 2023

• 09:2909:29, 17 August 2023 diff hist +23‎ Keypad ‎No edit summary
• 09:2809:28, 17 August 2023 diff hist +2,746‎ N Keypad ‎ Created page with "The WonderSwan SoC features a 4 by 3 keypad matrix. == Scanning == Scanning is done via writing to and reading from port $B5. <pre> 7 bit 0 ---- ---- .iii oooo ||| ++++- Output rows (0-3) +++------ Input rows (4-6) </pre> The standard procedure is to read rows 4, 5 and 6 in order, shifting their values into one twelve-bit mask like so: <pre> 15 bit 0 ---- ---- ---- ---- .... 4444 5555 6666 </pre> Typical keypad scanning implementations introduce a d..."
• 09:1809:18, 17 August 2023 diff hist +128‎ I/O port map ‎ clarify keypad port

16 August 2023

• 22:3322:33, 16 August 2023 diff hist +40‎ m I/O port map ‎ Mono Shade LUT
• 22:3122:31, 16 August 2023 diff hist +17,163‎ N I/O port map ‎ Created page with "* Superscripts are used to mark ports specific to a given mode or platform: ** Color mode: ^(color). ** WS/WSC/SC console: ^(WS), ^(WSC), ^(SC). * If two Bits rows are provided, the second one refers to the "Color" mode. * The Type can be: R - readable, W - writable, L - writable before boot ROM lockout, 8/16 - width (byte/word). {| class="wikitable" ! Category ! Port ! Description ! Bits ! Type ! Notes |- ! rowspan="45" | Displ..."

15 August 2023

• 13:2113:21, 15 August 2023 diff hist −1‎ m WSdev Wiki ‎No edit summary
• 13:2113:21, 15 August 2023 diff hist +35‎ WSdev Wiki ‎ add more URLs
• 13:1913:19, 15 August 2023 diff hist +26‎ WSdev Wiki ‎ add EEPROM, Mapper URLs
• 13:1713:17, 15 August 2023 diff hist +998‎ N Timing ‎ Created page with "== Clocks == The WonderSwan is clocked with a master clock of approximately 12288000 Hz (= 12.288 MHz). This clock is split into four internal memory access quadrants, running at 3072000 Hz (= 3.072 MHz) each. Three of those are used by the console in "mono" mode: NEC V30MZ, Display and Sound. On the WonderSwan Color, the fourth quadrant is used to handle color palette reads during display drawing. Out of those, only the CPU quadrant can access the car..."
• 13:1013:10, 15 August 2023 diff hist +13‎ WSdev Wiki ‎ add timing sub-page
• 06:1906:19, 15 August 2023 diff hist +8‎ WonderWitch .fx files ‎ clarify padding format
• 06:1806:18, 15 August 2023 diff hist −1‎ m ROM header ‎ fix typo
• 06:1806:18, 15 August 2023 diff hist −38‎ m ROM header ‎ remove references in ROM type section
• 06:1706:17, 15 August 2023 diff hist +1,382‎ N WonderWitch .fx files ‎ Created page with "FreyaOS uses XMODEM transfers to send and receive files through the serial port. These transfers do not include any file metadata by default - such as the file's name, size, permissions or creation date. As such, .fx files are used - binary files with a special 128-byte header<ref>XMODEM transfers are performed in 128-byte blocks; this allows fetching the file's metadata as the first block</ref>. == Format == {| class="wikitable" |+ Header contents |- ! Offset..."
• 06:0906:09, 15 August 2023 diff hist +91‎ WSdev Wiki ‎ add start of WonderWitch section
• 06:0406:04, 15 August 2023 diff hist +4,302‎ N ROM header ‎ Created page with "Every WonderSwan ROM contains a header. It is stored at the end - final sixteen bytes - of the ROM image. == ROM header == Parts of this header are validated or otherwise used by the console's boot ROM - they are marked in '''bold'''. {| class="wikitable" |+ Header contents |- ! Offset !! Length !! Contents |- | '''$0''' || '''5''' || Far jump instruction: '''0xEA''', offset, segment. |- | '''$5''' || '''1''' || '''Maintenance''' |- | $6 || 1 || Developer/Publishe..."
• 05:1605:16, 15 August 2023 diff hist +885‎ WSdev Wiki ‎ Initial landing page.