User contributions for Asie
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19 October 2024
- 19:0119:01, 19 October 2024 diff hist +41 WSdev Wiki →WonderWitch
- 17:1217:12, 19 October 2024 diff hist +117 WonderWitch/IL No edit summary current
- 12:5112:51, 19 October 2024 diff hist +591 N WonderWitch/IL/IlibIL Created page with "IlibIL is a library used to load other indirect libraries present on the system. == Functions == === open === <code>int open(const char far *name, IL far *buffer);</code> Load the specified IL <code>name</code> from <code>/rom0</code> or <code>/kern</code>. The IL header is copied to the provided <code>buffer</code> with addresses appropriately relocated to match the IL's location in ROM. === open_system === <code>int open_system(const char far *name, IL far *buffe..." current
- 12:0512:05, 19 October 2024 diff hist +108 m WonderWitch/FreyaOS →Revisions current
- 12:0512:05, 19 October 2024 diff hist +252 WonderWitch/FreyaOS add FreyaOS 1.1.2 and 1.1.3 changelog information
- 12:0112:01, 19 October 2024 diff hist +456 N WonderWitch/IL/ResumeIL Created page with "== ResumeIL == ResumeIL is a library which augments the process suspend/resume functionality of the built-in ProcIL library to also archive the memory areas <code>0x4000 - 0xBFFF</code> (WSC expanded/4bpp tile memory) and <code>0xFE00 - 0xFFFF</code> (WSC palette memory). This is done by copying this memory to <code>/ram0/resume.dat</code>. === Limitations === - This approach only allows suspending and resuming one process." current
- 11:1911:19, 19 October 2024 diff hist +1,837 N WonderWitch/FreyaBIOS/Timer Created page with "The Timer interrupt provides an abstraction layer for the WonderSwan's timers, as well as the on-cartridge RTC. == Types == === RTC fields === The RTC field indexes match the order of fields returned by the RTC chip. Note that FreyaBIOS transparently converts the values to and from BCD. {| class="wikitable" |- ! Index !! Data !! Format |- | 0 || Year || 0 - 99; 0 is assumed to be the year 2000. |- | 1 || Month || 1 - 12 |- | 2 || Date..."
- 07:5107:51, 19 October 2024 diff hist +27 WonderWitch/Process →Launching procedure current
18 October 2024
- 18:1118:11, 18 October 2024 diff hist +5 WonderWitch/Process →Compiler IDs
- 18:0218:02, 18 October 2024 diff hist +2,499 N WonderWitch/Process Created page with "== Memory layout == Process memory is stored in SRAM banks 3 (process 0 - typically used by FreyaOS), 2 (process 1) and 1 (process 2). The entire bank is available to the process. === Process control block === The process control block contains information about the running process. It is stored in the first 96 bytes of data. {| class="wikitable" |+ Process control block structure |- ! Offset !! Length !! Contents |- | 0 || 4 || Compiler ID, zero-terminated string; s..."
- 17:4617:46, 18 October 2024 diff hist −6 WSdev Wiki →WonderWitch
- 16:0216:02, 18 October 2024 diff hist −40 WonderWitch/IL →Header
- 15:5315:53, 18 October 2024 diff hist +2,364 N WonderWitch/IL Created page with "Indirect libraries (IL) are a FreyaOS feature designed to work around the 64KB segment limit of applications by offloading helper functionality to separate library binaries. == Calling convention == All functions exposed by an IL use the standard 8086 C calling convention - cdecl. * The stack is allocated and cleaned by the caller. * <code>AX</code>, <code>BX</code>, <code>CX</code>, <code>DX</code> can be modified freely by the callee. All other registers must be res..."
- 15:3315:33, 18 October 2024 diff hist +85 WSdev Wiki →WonderWitch
17 October 2024
- 14:2214:22, 17 October 2024 diff hist +42 WSdev Wiki →WonderWitch
- 14:2114:21, 17 October 2024 diff hist −744 WonderWitch .fx files No edit summary current
- 14:2114:21, 17 October 2024 diff hist +1,507 N WonderWitch/Filesystem Created page with "== Mount points == {| class="wikitable" |+ FreyaOS mount points |- ! Path !! File data location !! File table location !! File table size (entries) !! Description |- | <code>/rom0</code> || ROM (384 KB) || SRAM bank 3, $16F2 || 128 || |- | <code>/ram0</code> || SRAM bank 0 (64 KB) || SRAM bank 3, $06F2 || 64 || |- | <code>/</code> || || SRAM bank 3, $02F2 || 16 || |} == File table entry format == {| class="wikitable" |+ Header contents |- ! Offset !! Length !! Conten..." current
16 October 2024
- 15:2515:25, 16 October 2024 diff hist 0 m WonderWitch/FreyaBIOS/Text Fix typo
13 September 2024
- 14:3814:38, 13 September 2024 diff hist 0 I/O port map →I/O port map: fix typo current
- 14:3414:34, 13 September 2024 diff hist +20 m Display →LCD Status ($1A)
- 14:2714:27, 13 September 2024 diff hist +341 Display →LCD Control ($14)
- 14:2614:26, 13 September 2024 diff hist +614 Display →LCD Status ($1A)
- 14:1914:19, 13 September 2024 diff hist +61 Sound No edit summary current
- 14:1914:19, 13 September 2024 diff hist +161 I/O port map No edit summary
- 14:1714:17, 13 September 2024 diff hist +669 Sound No edit summary
10 September 2024
- 19:4019:40, 10 September 2024 diff hist −46 Sound →Sound Test ($95)
- 19:1519:15, 10 September 2024 diff hist +48 DMA →General DMA current
9 September 2024
- 17:0017:00, 9 September 2024 diff hist +165 DMA →General DMA
25 August 2024
22 August 2024
- 13:1113:11, 22 August 2024 diff hist +109 Interrupts →Interrupt Enable ($B2) current
- 13:1013:10, 22 August 2024 diff hist +238 Interrupts →Interrupts
21 August 2024
- 14:1714:17, 21 August 2024 diff hist +270 Display →Sprites
15 August 2024
- 08:0108:01, 15 August 2024 diff hist 0 m Display →Display Control ($00)
- 08:0108:01, 15 August 2024 diff hist 0 Display →Display Control ($00): fix bit order
- 08:0108:01, 15 August 2024 diff hist 0 I/O port map →I/O port map: fix $00 bit order
- 07:5707:57, 15 August 2024 diff hist +1,561 N NEC V30MZ interrupts Created page with "The NEC V30MZ provides six of the eight interrupts provided by the 80186. == Interrupts == === INT 0 - Divide Error === This interrupt is emitted as the result of a DIV<sup>IDIV</sup> or DIVU<sup>DIV</sup> instruction. === INT 1 - Single Step/Break === This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interru..." current
5 August 2024
- 09:3809:38, 5 August 2024 diff hist −4,729 NEC V30MZ move sections out to sub-pages current
- 09:3609:36, 5 August 2024 diff hist −25 m NEC V30MZ registers →NEC V30MZ registers current
- 09:3609:36, 5 August 2024 diff hist +2,141 N NEC V30MZ registers Created page with "= NEC V30MZ registers = * Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers: ** '''AX'''<sup>AW</sup> ('''AL''', '''AH''') - the ''accumulator'' register, ** '''BX'''<sup>BW</sup> ('''BL''', '''BH''') - the ''base'' register, ** '''CX'''<sup>CW</sup> ('''CL''', '''CH''') - the ''count'' register, ** '''DX'''<sup>DW</sup> ('''DL''', '''DH''') - the ''data'' register, * Four additional 16-bit registers: *..."
- 09:3609:36, 5 August 2024 diff hist +2,326 N NEC V30MZ flags Created page with " = NEC V30MZ flags = == Layout == The V30MZ processor features a 16-bit flag register: 15 bit 8 7 bit 0 ---- ---- ---- ---- m111 odit sz0a 0p1c | |||| || | | | | |||| || | | +- Carry (CF<sup>CY</sup>) | |||| || | +--- Parity (PF<sup>P</sup>) | |||| || +------ Auxillary Carry (AF<sup>AC</sup>) | |||| |+-------- Zero (Z) | |||| +--------- Sign (S) | |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>)..." current
- 09:2709:27, 5 August 2024 diff hist +310 EEPROM →Internal EEPROM Layout: figure out bytes 0x80, 0x81, 0x82
- 08:4908:49, 5 August 2024 diff hist +35 EEPROM fix error in internal EEPROM data layout
3 August 2024
- 09:0209:02, 3 August 2024 diff hist +11 NEC V30MZ No edit summary
- 09:0209:02, 3 August 2024 diff hist +63 m NEC V30MZ →Architecture
- 09:0109:01, 3 August 2024 diff hist +210 NEC V30MZ →Registers: add register names
- 07:2707:27, 3 August 2024 diff hist +1,504 NEC V30MZ →Flags: elaborate
2 August 2024
- 19:0119:01, 2 August 2024 diff hist −11 m NEC V30MZ fix formatting
- 18:3018:30, 2 August 2024 diff hist +1,033 NEC V30MZ →Registers
- 18:1818:18, 2 August 2024 diff hist +2,117 NEC V30MZ add architecture, sketch instruction set
- 16:5816:58, 2 August 2024 diff hist +2 m Cartridge connector →Signal descriptions: linear -> physical current
