NEC V30MZ interrupts

CPU interrupts

The NEC V30MZ implements six of the eight CPU interrupts provided by the 80186.

INT 0 - Divide Error

This interrupt is emitted as the result of a DIV^IDIV or DIVU^DIV instruction.

INT 1 - Single Step/Break

This interrupt is emitted if the single step flag is set after executing an instruction. (The instruction which changed the single step flag is ignored.) The single step flag is cleared for the duration of the interrupt, allowing the user to store state and perform debug activities; it is then restored when returning from the interrupt, by restoring the original processor flags stored on the stack.

INT 2 - Non-Maskable interrupt (NMI)

This interrupt is emitted when the SoC requests a non-maskable interrupt. On the WonderSwan, the condtions for emitting an NMI are configured by the relevant I/O port.

INT 3 - Breakpoint

This interrupt is emitted by the INT 3^BRK instruction. Unlike other unconditional interrupt instructions, it is encoded with only one byte.

INT 4 - Overflow

This interrupt is emitted by the INTO^BRKV instruction, if the overflow flag is set while it is being executed.

INT 5 - Array Bounds

This interrupt is emitted only by the BOUND^CHKIND instruction.

External interrupts

The NEC V30MZ distinguishes three sources of external interrupts - that is, interrupts not triggered by an instruction itself:

• Non-maskable interrupts:
  • NMI - controlled by the NMI control I/O port on WS,
  • BRK - controlled by the single-step flag.
• Maskable interrupts:
  • IRQ - controlled by the IRQ control I/O ports on WS.

Timing

Both non-maskable and maskable interrupts are acknowledged after the execution of an instruction is complete. However, under some conditions, interrupts may not be processed on a given instruction and delayed until the next one. This is the case for:

• instructions which change the stack segment register (MOV and POP),
• prefix instructions (LOCK, REP, segment prefixes),
• instructions which set the interrupt enable CPU flag (STI, POPF), if the flag was cleared prior to the instruction's execution (for IRQ interrupts only),
• instructions which set the single-step CPU flag, if the flag was cleared prior to the instruction's execution (for BRK interrupts only).

TODO: Document how many cycles interrupt processing takes.

Notes

• The following 80186 interrupts are not implemented:
  • INT 6 - Unused Opcode - the V30MZ treats most unimplemented instructions as NOPs.
  • INT 7 - ESC Opcode - the V30MZ, likewise, treats these instructions as NOPs.