Bandai 2003

In addition to the normal Mapper banking interface, Bandai's 2003 adds registers for an RTC interface, GPO pins, self flashing, and accessing more than 16MiB of ROM.

Category	Port	Description	Bits	Type	Notes
RTC	$CA	RTC Command	...1 CCCC	W8	Command (C)
		RTC Status	D00B CCCC	R8	Busy (B), Command (C), Data needed (D)
	$CB	RTC Payload	dddd dddd	RW8	Data (d)
GPO	$CC	GPO Data Direction	0000 oooo	RW8	1 = output, 0 = high-impedance (weak pull-down)
	$CD	GPO Data	0000 dddd	RW8	1 = 3V, if enabled by data direction
Self-Flash	$CE	Self-Flash Control	0000 000r	RW8	1 = ROM is accessible at segment 0x1000; 0 = RAM instead.
Extended bankswitching	$CF	ROM Linear (EX) Bank	00bb bbbb	RW8	Selects a 1MiB bank accessed via segments 0x4000 through 0xF000. Identical to the register at 0xC0.
	$D0	RAM(/ROM) Bank	0000 00bb bbbb bbbb	RW16	Selects a 64KiB bank accessed via segment 0x1000. Lower 8 bits are identical to the register at 0xC1.
	$D2	ROM0 Bank	0000 00bb bbbb bbbb	RW16	Selects a 64KiB bank accessed via segment 0x2000. Lower 8 bits are identical to the register at 0xC2.
	$D4	ROM1 Bank	0000 00bb bbbb bbbb	RW16	Selects a 64KiB bank accessed via segment 0x3000. Lower 8 bits are identical to the register at 0xC3.

Not all PCBs are wired to support self-flashing. Not all ROMs have the needed /BYTE pin. Even on PCBs without support, ROM can still be enabled by writing to port $CE.

2003 RTC interface

The 2003's RTC interface is a simple half-duplex SPI-like protocol. A write to $CA will start a transaction, depending on the exact value written.

For specifics of what the S-3511A expects to be done with these bytes, see Real-Time Clock.

(Put logic analyzer traces here)

Values are as follows:

$00-$0F, $1C-$1F

Immediately stop the transaction. This cannot be safely used to abort an ongoing transaction, because the 2003 still relays the 384kHz clock. In contrast, normal termination stops relaying that clock.

$10, $11

Send command byte ($60 or $61 respectively) and stop.

$12

Send command byte ($62), then send byte stored in $CB, then stop. The 2003 expects that the value in $CB is valid and does not pause if the CPU hasn't yet written a value.

$13

Send command byte ($63), then receive byte, then stop. After the "data needed" is set or the "busy" bit is clear the value can be read from $CB.

$14

Send command byte ($64), then send seven bytes of payload, then stop. The 2003 expects that the first byte is preloaded in $CB, but pauses for the CPU to write each subsequent byte by setting the "Data needed" bit.

$15

Send command byte ($65), then receive seven bytes of payload, then stop. The 2003 pauses for the CPU to read each subsequent byte by setting the "Data needed" bit.

$16

Send command byte ($66), then send three bytes of payload, then stop.bit.

$17

Send command byte ($67), then receive three bytes of payload, then stop.

$18, $1A

Send command byte ($68 or $6A), then send two bytes of payload, then stop.needed" bit.

$19, $1B

Send command byte ($69 or $6B), then receive two bytes of payload, then stop.