NEC V30MZ instruction set: Difference between revisions

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{{Anchor|DEC}}
{{Anchor|DEC}}
=== DEC ===
=== DEC ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DEC mem8 || <tt>FE /1</tt> || <tt>11111110 oo001mmm</tt> || 2+ || 3
|-
| DEC mem16 || <tt>FF /1</tt> || <tt>11111111 oo001mmm</tt> || 2+ || 3
|-
| DEC reg8 || <tt>FE /1</tt> || <tt>11111110 11001mmm</tt> || 2+ || 1
|-
| DEC reg16 || <tt>4x</tt> || <tt>01001rrr</tt> || 1 || 1
|}


----
----
{{Anchor|DIV}}
{{Anchor|DIV}}
=== DIV ===
=== DIV ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DIV mem8 || <tt>F6 /6</tt> || <tt>11110110 oo110mmm</tt> || 2+ || 16
|-
| DIV mem16 || <tt>F7 /6</tt> || <tt>11111111 oo110mmm</tt> || 2+ || 24
|-
| DIV reg8 || <tt>F6 /6</tt> || <tt>11111110 11110mmm</tt> || 2+ || 15
|-
| DIV reg16 || <tt>F7 /6</tt> || <tt>11111111 11110mmm</tt> || 2+ || 23
|}


----
----
{{Anchor|DS}}
{{Anchor|DS}}
=== DS ===
=== DS ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| DS || <tt>3E</tt> || <tt>00111110</tt> || 1 || 1
|}


----
----
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{{Anchor|ES}}
{{Anchor|ES}}
=== ES ===
=== ES ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| ES || <tt>26</tt> || <tt>00100110</tt> || 1 || 1
|}


----
----
{{Anchor|HLT}}
{{Anchor|HLT}}
=== HLT ===
=== HLT ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| HLT || <tt>F4</tt> || <tt>11110100</tt> || 1 || 9
|}


----
----
{{Anchor|IDIV}}
{{Anchor|IDIV}}
=== IDIV ===
=== IDIV ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IDIV mem8 || <tt>F6 /7</tt> || <tt>11110110 oo111mmm</tt> || 2+ || 18
|-
| IDIV mem16 || <tt>F7 /7</tt> || <tt>11111111 oo111mmm</tt> || 2+ || 25
|-
| IDIV reg8 || <tt>F6 /7</tt> || <tt>11111110 11111mmm</tt> || 2+ || 17
|-
| IDIV reg16 || <tt>F7 /7</tt> || <tt>11111111 11111mmm</tt> || 2+ || 24
|}


----
----
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{{Anchor|IN}}
{{Anchor|IN}}
=== IN ===
=== IN ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| IN AL, DX || <tt>EC</tt> || <tt>11101100</tt> || 1 || 6
|-
| IN AX, DX || <tt>ED</tt> || <tt>11101101</tt> || 1 || 6
|-
| IN AL, imm8 || <tt>E4 ii</tt> || <tt>11100100 iiiiiiii</tt> || 2 || 6
|-
| IN AX, imm8 || <tt>E5 ii</tt> || <tt>11100101 iiiiiiii</tt> || 2 || 6
|}


----
----
{{Anchor|INC}}
{{Anchor|INC}}
=== INC ===
=== INC ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| INC mem8 || <tt>FE /0</tt> || <tt>11111110 oo000mmm</tt> || 2+ || 3
|-
| INC mem16 || <tt>FF /0</tt> || <tt>11111111 oo000mmm</tt> || 2+ || 3
|-
| INC reg8 || <tt>FE /0</tt> || <tt>11111110 11000mmm</tt> || 2+ || 1
|-
| INC reg16 || <tt>4x</tt> || <tt>01000rrr</tt> || 1 || 1
|}


----
----
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{{Anchor|LEAVE}}
{{Anchor|LEAVE}}
=== LEAVE ===
=== LEAVE ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LEAVE || <tt>C9</tt> || <tt>11001001</tt> || 1 || 2
|}


----
----
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{{Anchor|LOOP}}
{{Anchor|LOOP}}
=== LOOP ===
=== LOOP ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOP rel8 || <tt>E2 ii</tt> || <tt>11100010 iiiiiiii</tt> || 2 || 2 (5 if branch taken)
|}


----
----
{{Anchor|LOOPE}}
{{Anchor|LOOPE}}
=== LOOPE ===
=== LOOPE ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPE rel8 || <tt>E1 ii</tt> || <tt>11100001 iiiiiiii</tt> || 2 || 3 (6 if branch taken)
|}


----
----
{{Anchor|LOOPNE}}
{{Anchor|LOOPNE}}
=== LOOPNE ===
=== LOOPNE ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| LOOPNE rel8 || <tt>E0 ii</tt> || <tt>11100000 iiiiiiii</tt> || 2 || 3 (6 if branch taken)
|}


----
----
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{{Anchor|OUT}}
{{Anchor|OUT}}
=== OUT ===
=== OUT ===
{| class="wikitable sortable"
! Instruction !! Opcode (hex) !! Opcode (bin) !! Bytes !! Cycles
|-
| OUT AL, DX || <tt>EE</tt> || <tt>11101110</tt> || 1 || 6
|-
| OUT AX, DX || <tt>EF</tt> || <tt>11101111</tt> || 1 || 6
|-
| OUT AL, imm8 || <tt>E6 ii</tt> || <tt>11100110 iiiiiiii</tt> || 2 || 6
|-
| OUT AX, imm8 || <tt>E7 ii</tt> || <tt>11100111 iiiiiiii</tt> || 2 || 6
|}


----
----

Revision as of 21:27, 27 December 2024


Note that this page is a work in progress.

Official V30MZ (80186) Instructions
AAA AAD AAM AAS ADC ADD AND BOUND CALL CBW CLC
CLD CLI CMC CMP CMPSB CMPSW CS CWD DAA DAS DEC
DIV DS ENTER ES HLT IDIV IMUL IN INC INSB INSW
INT INTO IRET JA JBE JC JCXZ JG JGE JL JLE
JMP JNC JNO JNP JNS JNZ JO JP JS JZ LAHF
LDS LEA LEAVE LES LOCK LODSB LODSW LOOP LOOPE LOOPNE MOV
MOVSB MOVSW MUL NEG NOP NOT OR OUT OUTSB OUTSW POLL
POP POPA POPF PUSH PUSHA PUSHF RCL RCR REP REPNE RET
RETF ROL ROR SAHF SAR SBB SCASB SCASW SHL SHR SS
STC STD STI STOSB STOSW SUB TEST XCHG XLAT XOR
Intel <-> NEC mnemonic translation table
Intel NEC
AAA ADJBA
AAD CVTDB
AAM CVTBD
AAS ADJBS
ADC ADDC
ADD ADD
AND AND
BOUND CHKIND
CALL CALL
CBW CVTBW
CLC CLR1 CY
CLD CLR1 DIR
CLI DI
CMC NOT1 CY
CMP CMP
CMPSB CMPBKB
CMPSW CMPBKW
CS PS
CWD CVTWL
DAA ADJ4A
DAS ADJ4S
DEC DEC
DIV DIVU
DS DS0
ENTER PREPARE
ES DS1
HLT HALT
IDIV DIV
IMUL MUL
IN IN
INC INC
INSB INMB
INSW INMW
INT BRK
INTO BRKV
IRET RETI
JA BH
JBE BNH
JC/JB BC/BL
JCXZ BCWZ
JG BGT
JGE BGE
JL BLT
JLE BLE
JMP BR
JNC/JAE BNC/BNL
JNO BNV
JNP BPO
JNS BP
JNZ/JNE BNZ/BNE
JO BV
JP BPE
JS BN
JZ/JE BZ/BE
LAHF MOV
LDS MOV
LEA LDEA
LEAVE DISPOSE
LES MOV
LOCK BUSLOCK
LODSB LDMB
LODSW LDMW
LOOP DBNZ
LOOPE DBNZE
LOOPNE DBNZNE
MOV MOV
MOVSB MOVBKB
MOVSW MOVBKW
MUL MULU
NEG NEG
NOP NOP
NOT NOT
OR OR
OUT OUT
OUTSB OUTM
OUTSW OUTM
POLL POLL
POP POP
POPA POP
POPF POP
PUSH PUSH
PUSHA PUSH
PUSHF PUSH
RCL ROLC
RCR RORC
REP/REPE/REPZ REP/REPE/REPZ
REPNE/REPNZ REPNE/REPNZ
RET RET
RETF RET
ROL ROL
ROR ROR
SAHF MOV
SAR SHRA
SBB SUBC
SCASB CMPMB
SCASW CMPMW
SHL SHL
SHR SHR
SS SS
STC SET1 CY
STD SET1 DIR
STI EI
STOSB STMB
STOSW STMW
SUB SUB
TEST TEST
XCHG XCH
XLAT TRANS
XOR XOR

Official instructions by type

Type Instructions
Memory MOV XCHG XLAT LEA LDS LES IN OUT
Ports IN OUT INSB OUTSB INSW OUTSW
Arithmetic ADD SUB ADC SBB INC DEC MUL DIV IMUL IDIV CMP NEG
Numeric CBW CWD AAA AAS AAM AAD DAA DAS
Shift ROL ROR RCL RCR SHL SHR SAR
Bitwise AND OR XOR NOT TEST
Branch JC JNC JZ JNZ JBE JA JO JNO JP JNP JS JNS JL JGE JLE JG
Jump JMP CALL RET RETF
Loop LOOP LOOPE LOOPNE
Interrupt INT IRET INTO HLT BOUND
Stack PUSH POP PUSHA POPA PUSHF POPF
Flags CLC STC CLD STD CLI STI CMC LAHF SAHF
Prefix CS DS ES SS
String REP REPE REPNE MOVSB MOVSW LODSB STOSB LODSW STOSW CMPSB SCASB CMPSW SCASW
Other NOP ENTER LEAVE LOCK POLL

Instruction encoding

ModR/M byte

The ModR/M byte is used in most addressing modes which reference a memory location. This byte consists of three bitfield values:

  • oo - Mode;
  • rrr - Two possible functions:
    • Register (for addressing modes which require both a register and a register/memory operand),
    • Opcode extension (for some opcodes' addressing modes which do not have such a requirement);
  • mmm - Register/Memory.

The Mode and Register/Memory bitfields can refer to a memory location or to a register, as shown in the table below. In some addressing modes, the Register field also refers to a register; it is always interpreted as if Mode was equal to 11.

R/M \ Mode 00 01 10 11 (byte) 11 (word)
000 DS:[BX + SI] DS:[BX + SI + disp8] DS:[BX + SI + disp16] AL AX
001 DS:[BX + DI] DS:[BX + DI + disp8] DS:[BX + DI + disp16] CL CX
010 SS:[BP + SI] SS:[BP + SI + disp8] SS:[BP + SI + disp16] DL DX
011 SS:[BP + DI] SS:[BP + DI + disp8] SS:[BP + DI + disp16] BL BX
100 DS:[SI] DS:[SI + disp8] DS:[SI + disp16] AH SP
101 DS:[DI] DS:[DI + disp8] DS:[DI + disp16] CH BP
110 DS:[disp16] SS:[BP + disp8] SS:[BP + disp16] DH SI
111 DS:[BX] DS:[BX + disp8] DS:[BX + disp16] BH DI

Displacements are either 8-bit (disp8) or 16-bit (disp16) signed values and they always immediately follow the ModR/M byte. Note that (oo = 00, mmm = 110) is a special case, in which the disp16 value is used directly as a near pointer.

The instruction encoding lists below refer to this byte as oorrrmmm (binary), /r (hexadecimal) or /0 (hexademical, rrr used as function 0).

Official instructions

AAA

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
AAA 37 00110111 1 9

AAD

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
AAD imm8 B5 ii 11010100 iiiiiiii 2 6

AAM

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
AAM imm8 B4 ii 11010100 iiiiiiii 2 17

AAS

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
AAS 3F 00111111 1 9

ADC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
ADC AL, imm 14 ii 00010100 iiiiiiii 2 1
ADC AX, imm 15 ii ii 00010101 iiiiiiii iiiiiiii 3 1
ADC mem8, imm8 80 /2 ii 10000000 oo010mmm iiiiiiii 3+ 3
ADC mem16, imm16 81 /2 ii ii 10000001 oo010mmm iiiiiiii iiiiiiii 4+ 3
ADC mem16, simm8 83 /2 ii ii 10000011 oo010mmm iiiiiiii iiiiiiii 4+ 3
ADC mem8, reg8 10 /r 00010000 oorrrmmm 2+ 3
ADC mem16, reg16 11 /r 00010001 oorrrmmm 2+ 3
ADC reg8, imm8 80 /2 ii 10000000 11010mmm iiiiiiii 3+ 1
ADC reg16, imm16 81 /2 ii ii 10000001 11010mmm iiiiiiii iiiiiiii 4+ 1
ADC reg16, simm8 83 /2 ii ii 10000011 11010mmm iiiiiiii iiiiiiii 4+ 1
ADC reg8, mem8 12 /r 00010010 oorrrmmm 2+ 2
ADC reg16, mem16 13 /r 00010011 oorrrmmm 2+ 2
ADC reg8, reg8 10 /r 000100.0 11rrrmmm 2 1
ADC reg16, reg16 11 /r 000100.1 11rrrmmm 2 1

ADD

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
ADD AL, imm 04 ii 00000100 iiiiiiii 2 1
ADD AX, imm 05 ii ii 00000101 iiiiiiii iiiiiiii 3 1
ADD mem8, imm8 80 /0 ii 10000000 oo000mmm iiiiiiii 3+ 3
ADD mem16, imm16 81 /0 ii ii 10000001 oo000mmm iiiiiiii iiiiiiii 4+ 3
ADD mem16, simm8 83 /0 ii ii 10000011 oo000mmm iiiiiiii iiiiiiii 4+ 3
ADD mem8, reg8 00 /r 00000000 oorrrmmm 2+ 3
ADD mem16, reg16 01 /r 00000001 oorrrmmm 2+ 3
ADD reg8, imm8 80 /0 ii 10000000 11000mmm iiiiiiii 3+ 1
ADD reg16, imm16 81 /0 ii ii 10000001 11000mmm iiiiiiii iiiiiiii 4+ 1
ADD reg16, simm8 83 /0 ii ii 10000011 11000mmm iiiiiiii iiiiiiii 4+ 1
ADD reg8, mem8 02 /r 00000010 oorrrmmm 2+ 2
ADD reg16, mem16 03 /r 00000011 oorrrmmm 2+ 2
ADD reg8, reg8 00 /r 000000.0 11rrrmmm 2 1
ADD reg16, reg16 01 /r 000000.1 11rrrmmm 2 1

AND

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
AND AL, imm 24 ii 00100100 iiiiiiii 2 1
AND AX, imm 25 ii ii 00100101 iiiiiiii iiiiiiii 3 1
AND mem8, imm8 80 /4 ii 10000000 oo100mmm iiiiiiii 3+ 3
AND mem16, imm16 81 /4 ii ii 10000001 oo100mmm iiiiiiii iiiiiiii 4+ 3
AND mem16, simm8 83 /4 ii ii 10000011 oo100mmm iiiiiiii iiiiiiii 4+ 3
AND mem8, reg8 20 /r 00100000 oorrrmmm 2+ 3
AND mem16, reg16 21 /r 00100001 oorrrmmm 2+ 3
AND reg8, imm8 80 /4 ii 10000000 11100mmm iiiiiiii 3+ 1
AND reg16, imm16 81 /4 ii ii 10000001 11100mmm iiiiiiii iiiiiiii 4+ 1
AND reg16, simm8 83 /4 ii ii 10000011 11100mmm iiiiiiii iiiiiiii 4+ 1
AND reg8, mem8 22 /r 00100010 oorrrmmm 2+ 2
AND reg16, mem16 23 /r 00100011 oorrrmmm 2+ 2
AND reg8, reg8 20 /r 001000.0 11rrrmmm 2 1
AND reg16, reg16 21 /r 001000.1 11rrrmmm 2 1

BOUND

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
BOUND reg16, mem16:16 62 /r 01100010 oorrrmmm 2+ 13 (20 if condition met)

CALL

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CALL ptr16:16 CA oo oo ss ss 10011010 oooooooo oooooooo ssssssss ssssssss 5 10
CALL mem16 FF /2 11111111 oo010mmm 2+ 6
CALL mem16:16 FF /3 11111111 oo011mmm 2+ 12
CALL reg16 FF /2 11111111 11010mmm 2 5
CALL rel16 E8 ii ii 11101000 iiiiiiii iiiiiiii 3 5

CBW

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CBW 98 10011000 1 1

CLC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CLC F8 11111000 1 4

CLD

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CLD FC 11111100 1 4

CLI

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CLI FA 11111010 1 4

CMC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CMC F5 11110101 1 4

CMP

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CMP AL, imm 3C ii 00111100 iiiiiiii 2 1
CMP AX, imm 3D ii ii 00111101 iiiiiiii iiiiiiii 3 1
CMP mem8, imm8 80 /7 ii 10000000 oo111mmm iiiiiiii 3+ 2
CMP mem16, imm16 81 /7 ii ii 10000001 oo111mmm iiiiiiii iiiiiiii 4+ 2
CMP mem16, simm8 83 /7 ii ii 10000011 oo111mmm iiiiiiii iiiiiiii 4+ 2
CMP mem8, reg8 38 /r 00111000 oorrrmmm 2+ 2
CMP mem16, reg16 39 /r 00111001 oorrrmmm 2+ 2
CMP reg8, imm8 80 /7 ii 10000000 11111mmm iiiiiiii 3+ 1
CMP reg16, imm16 81 /7 ii ii 10000001 11111mmm iiiiiiii iiiiiiii 4+ 1
CMP reg16, simm8 83 /7 ii ii 10000011 11111mmm iiiiiiii iiiiiiii 4+ 1
CMP reg8, mem8 3A /r 00111010 oorrrmmm 2+ 2
CMP reg16, mem16 3B /r 00111011 oorrrmmm 2+ 2
CMP reg8, reg8 38 /r 001110.0 11rrrmmm 2 1
CMP reg16, reg16 39 /r 001110.1 11rrrmmm 2 1

CMPSB

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CMPSB A6 10100110 1 6

CMPSW

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CMPSW A7 10100111 1 6

CS

CWD

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
CWD 99 10011001 1 1

DAA

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
DAA 27 00100111 1 10

DAS

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
DAS 2F 00101111 1 10

DEC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
DEC mem8 FE /1 11111110 oo001mmm 2+ 3
DEC mem16 FF /1 11111111 oo001mmm 2+ 3
DEC reg8 FE /1 11111110 11001mmm 2+ 1
DEC reg16 4x 01001rrr 1 1

DIV

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
DIV mem8 F6 /6 11110110 oo110mmm 2+ 16
DIV mem16 F7 /6 11111111 oo110mmm 2+ 24
DIV reg8 F6 /6 11111110 11110mmm 2+ 15
DIV reg16 F7 /6 11111111 11110mmm 2+ 23

DS

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
DS 3E 00111110 1 1

ENTER

ES

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
ES 26 00100110 1 1

HLT

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
HLT F4 11110100 1 9

IDIV

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
IDIV mem8 F6 /7 11110110 oo111mmm 2+ 18
IDIV mem16 F7 /7 11111111 oo111mmm 2+ 25
IDIV reg8 F6 /7 11111110 11111mmm 2+ 17
IDIV reg16 F7 /7 11111111 11111mmm 2+ 24

IMUL

IN

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
IN AL, DX EC 11101100 1 6
IN AX, DX ED 11101101 1 6
IN AL, imm8 E4 ii 11100100 iiiiiiii 2 6
IN AX, imm8 E5 ii 11100101 iiiiiiii 2 6

INC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
INC mem8 FE /0 11111110 oo000mmm 2+ 3
INC mem16 FF /0 11111111 oo000mmm 2+ 3
INC reg8 FE /0 11111110 11000mmm 2+ 1
INC reg16 4x 01000rrr 1 1

INSB

INSW

INT

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
INT 3 CC 11001100 1 9
INT imm8 CD ii 11001101 iiiiiiii 2 10

INTO

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
INTO CE 11001110 1 6 (13 if OF = 1)

IRET

JA

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JA rel8 77 ii 01110111 iiiiiiii 2 1 (4 if branch taken)

JBE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JA rel8 76 ii 01110110 iiiiiiii 2 1 (4 if branch taken)

JC/JB

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JC rel8 72 ii 01110010 iiiiiiii 2 1 (4 if branch taken)

JCXZ

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JCXZ rel8 E3 ii 11100011 iiiiiiii 2 1 (4 if branch taken)

JG

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JG rel8 7F ii 01111111 iiiiiiii 2 1 (4 if branch taken)

JGE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JGE rel8 7D ii 01111101 iiiiiiii 2 1 (4 if branch taken)

JL

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JL rel8 7C ii 01111100 iiiiiiii 2 1 (4 if branch taken)

JLE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JLE rel8 7E ii 01111110 iiiiiiii 2 1 (4 if branch taken)

JMP

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JMP ptr16:16 EA oo oo ss ss 11101010 oooooooo oooooooo ssssssss ssssssss 5 7
JMP mem16 FF /4 11111111 oo100mmm 2+ 5
JMP mem16:16 FF /5 11111111 oo101mmm 2+ 10
JMP reg16 FF /4 11111111 11100mmm 2 4
JMP rel8 EB ii 11101011 iiiiiiii 2 4
JMP rel16 E9 ii ii 11101001 iiiiiiii iiiiiiii 3 4

JNC/JAE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JNC rel8 73 ii 01110011 iiiiiiii 2 1 (4 if branch taken)

JNO

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JNO rel8 71 ii 01110001 iiiiiiii 2 1 (4 if branch taken)

JNP

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JNP rel8 7B ii 01111011 iiiiiiii 2 1 (4 if branch taken)

JNS

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JNS rel8 79 ii 01111001 iiiiiiii 2 1 (4 if branch taken)

JNZ/JNE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JNZ rel8 75 ii 01110101 iiiiiiii 2 1 (4 if branch taken)

JO

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JO rel8 70 ii 01110000 iiiiiiii 2 1 (4 if branch taken)

JP

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JP rel8 7A ii 01111010 iiiiiiii 2 1 (4 if branch taken)

JS

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JS rel8 78 ii 01111000 iiiiiiii 2 1 (4 if branch taken)

JZ/JE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
JZ rel8 74 ii 01110100 iiiiiiii 2 1 (4 if branch taken)

LAHF

LDS

LEA

LEAVE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
LEAVE C9 11001001 1 2

LES

LOCK

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
LOCK F0 11110000 1 1

LODSB

LODSW

LOOP

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
LOOP rel8 E2 ii 11100010 iiiiiiii 2 2 (5 if branch taken)

LOOPE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
LOOPE rel8 E1 ii 11100001 iiiiiiii 2 3 (6 if branch taken)

LOOPNE

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
LOOPNE rel8 E0 ii 11100000 iiiiiiii 2 3 (6 if branch taken)

MOV

MOVSB

MOVSW

MUL

NEG

NOP

NOT

OR

OUT

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
OUT AL, DX EE 11101110 1 6
OUT AX, DX EF 11101111 1 6
OUT AL, imm8 E6 ii 11100110 iiiiiiii 2 6
OUT AX, imm8 E7 ii 11100111 iiiiiiii 2 6

OUTSB

OUTSW

POLL

POP

POPA

POPF

PUSH

PUSHA

PUSHF

RCL

RCR

REP/REPE/REPZ

REPNE/REPNZ

RET

RETF

ROL

ROR

SAHF

SAR

SBB

SCASB

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
SCASB AE 10101110 1 4

SCASW

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
SCASW AF 10101111 1 4


SHL

SHR

SS

STC

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
STC F9 11111001 1 4

STD

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
STD FD 11111101 1 4

STI

Instruction Opcode (hex) Opcode (bin) Bytes Cycles
STI FB 11111011 1 4

STOSB

STOSW

SUB

TEST

XCHG

XLAT

XOR

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