Real-Time Clock: Difference between revisions

From WSdev Wiki
Jump to navigationJump to search
 
(One intermediate revision by the same user not shown)
Line 3: Line 3:
This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)
This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)


== Internal operation ==
== Registers ==
The RTC consists of 10 total bytes of user-visible state.
* Configuration
* Alarm configuration (2 bytes)
The following are always interpreted as 2 digit packed BCD.
* Year (always assumes 00 is a leap year)
* Month (1=January)
* Day-of-month (1-indexed)
* Day-of-week (0-indexed and free-running, no predefined mapping of number to legal day)
* Hour (0x80s bit is 12/24 state)
* Minute
* Second


=== Configuration ===
=== Configuration ===


  7  bit  0
  7  bit  0
  P2A0 M0F0
  ---- ----
p2a0 m0f0
|||  | |
||+--+-+-- Interrupt mode; see below
|+-------- 12/24 hour mode
|          - 0: 12 hour mode
|          - 1: 24 hour mode
+--------- Power failure occurred
 
Note that sending the Reset or Read Configuration commands clears the "power failure" bit.
 
==== Interrupt mode ====
 
{| class="wikitable"
! A
! M
! F
! Name
! Description
|-
| 0
| 0
| 0
| Disabled
| Continuously deasserts /IRQ pin.
|-
| 1
| 0
| 0
| Alarm
| Asserts /IRQ during the hour and minute set in the alarm configuration register.
|-
| rowspan="3" | x
| 0
| 1
| Frequency
| Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
|-
| 1
| 0
| Per-minute edge
| Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
|-
| 1
| 1
| Per-minute steady
| Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.
|}
 
=== Date/Time ===
 
The date and time is stored using seven bytes, of which the latter three correspond to the time.
 
==== Date ====
 
7  bit  0
---- ----  Byte 0
yyyy yyyy
  |||| ||||
  |||| ||||
  |||+--+-+--- always 0
  ++++-++++- Year (00 - 99, BCD)
  ||+--+-+---- IRQ mode
 
  |+---------- 1: 24 hour mode  0: 12 hour mode
7  bit  0
  +----------- power failure occurred
---- ----  Byte 1
...m mmmm
    | ||||
    +-++++- Month (01 - 12, BCD)
 
7  bit  0
---- ----  Byte 2
..dd dddd
  || ||||
  ++-++++- Day of month (01 - 31, BCD)
 
7  bit  0
---- ----  Byte 3
  .... .www
      |||
      +++- Day of week (0 - 6)
 
While this convention does not have to be followed, [[WonderWitch/FreyaBIOS|FreyaBIOS]] assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.
 
==== Time ====
 
7  bit  0
---- ---- Byte 4
p.hh hhhh
| || ||||
  | ++-++++- Hour (00 - 11 or 23, BCD)
+--------- 0 = AM, 1 = PM
 
In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour >= 12); however, writes to the bit are ignored.
 
7  bit  0
---- ----  Byte 5
.mmm mmmm
  ||| ||||
   +++-++++- Minute (00 - 59, BCD)
 
7  bit  0
---- ----  Byte 6
.sss ssss
  ||| ||||
  +++-++++- Second (00 - 59, BCD)
 
=== Alarm configuration ===
 
The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.
 
==== Interrupt mode: Alarm ====
 
7  bit  0
---- ----  Byte 0
p.hh hhhh
| || ||||
  | ++-++++- Hour to match for the alarm (BCD)
+--------- AM/PM bit to match for the alarm


Sending the Reset or Read Configuration commands clear the "power failure" bit.
bit 0
---- ----  Byte 1
.mmm mmmm
  ||| ||||
  +++-++++- Minute to match for the alarm (BCD)


Interrupts:
Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.
 
==== Interrupt mode: Frequency ====
 
7  bit  0
---- ----  Byte 0
abcd efgh
|||| ||||
|||| |||+- 32768 Hz
|||| ||+-- 16384 Hz
|||| |+---  8192 Hz
|||| +----  4096 Hz
|||+------  2048 Hz
||+-------  1024 Hz
|+--------  512 Hz
+---------  256 Hz
 
7  bit  0
---- ----  Byte 1
abcd efgh
|||| ||||
|||| |||+-  128 Hz
|||| ||+--    64 Hz
|||| |+---    32 Hz
|||| +----    16 Hz
|||+------    8 Hz
||+-------    4 Hz
|+--------    2 Hz
+---------    1 Hz


AMF
== Commands ==
000 -- "No interrupts" - continuously deasserts /IRQ pin
100 -- "Alarm" - Treat "alarm configuration" as packed BCD HHMM. Assert /IRQ during that hour and minute. Hour encoding must match 12/24 bit setting.
x10 -- "Per-minute edge" - Asserts /IRQ during the first 10 ms of each minute. During following 990ms, /IRQ can be deasserted by reading the configuration register.
x11 -- "Per-minute steady" - Asserts /IRQ during the first 10ms of each minute. De-asserts /IRQ at the 30th second.
x01 -- "Frequency" - subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.


=== Reset RTC ($10, $11) ===
=== Reset RTC ($10, $11) ===

Latest revision as of 15:17, 13 December 2024

The 2003 mapper provides a special-purpose interface to interact with Seiko's S-3511A RTC chip.

This page will cover how games expect to interact with it; not the low-level protocol specifics. (For that see the datasheet and the Timing section of this wiki)

Registers

Configuration

7  bit  0
---- ----
p2a0 m0f0
|||  | | 
||+--+-+-- Interrupt mode; see below
|+-------- 12/24 hour mode
|          - 0: 12 hour mode
|          - 1: 24 hour mode
+--------- Power failure occurred

Note that sending the Reset or Read Configuration commands clears the "power failure" bit.

Interrupt mode

A M F Name Description
0 0 0 Disabled Continuously deasserts /IRQ pin.
1 0 0 Alarm Asserts /IRQ during the hour and minute set in the alarm configuration register.
x 0 1 Frequency Subsecond prescaler is bitwise inverted, bitwise ANDed with the lower 15 bits of the "alarm configuration" register, then all fifteen bits are NORed together. This signal directly drives the /IRQ pin.
1 0 Per-minute edge Asserts /IRQ during the first 10 ms of each minute. During the following 990 ms, /IRQ can be deasserted by reading the configuration register.
1 1 Per-minute steady Asserts /IRQ during the first 10 ms of each minute. De-asserts /IRQ at the 30th second.

Date/Time

The date and time is stored using seven bytes, of which the latter three correspond to the time.

Date

7  bit  0
---- ----  Byte 0
yyyy yyyy
|||| ||||
++++-++++- Year (00 - 99, BCD)
7  bit  0
---- ----  Byte 1
...m mmmm
   | ||||
   +-++++- Month (01 - 12, BCD)
7  bit  0
---- ----  Byte 2
..dd dddd
  || ||||
  ++-++++- Day of month (01 - 31, BCD)
7  bit  0
---- ----  Byte 3
.... .www
      |||
      +++- Day of week (0 - 6)

While this convention does not have to be followed, FreyaBIOS assumes that the first day of the week (0) is a Sunday, (1) is a Monday, ... (6) is a Saturday.

Time

7  bit  0
---- ----  Byte 4
p.hh hhhh
| || ||||
| ++-++++- Hour (00 - 11 or 23, BCD)
+--------- 0 = AM, 1 = PM

In the 24-hour mode, reading the AM/PM bit returns correct values (set if hour >= 12); however, writes to the bit are ignored.

7  bit  0
---- ----  Byte 5
.mmm mmmm
 ||| ||||
 +++-++++- Minute (00 - 59, BCD)
7  bit  0
---- ----  Byte 6
.sss ssss
 ||| ||||
 +++-++++- Second (00 - 59, BCD)

Alarm configuration

The alarm configuration register is two bytes in size; its interpretation depends on the configured interrupt mode.

Interrupt mode: Alarm

7  bit  0
---- ----  Byte 0
p.hh hhhh
| || ||||
| ++-++++- Hour to match for the alarm (BCD)
+--------- AM/PM bit to match for the alarm
7  bit  0
---- ----  Byte 1
.mmm mmmm
 ||| ||||
 +++-++++- Minute to match for the alarm (BCD)

Note that the hour encoding of the alarm must match the hour encoding used by the clock itself.

Interrupt mode: Frequency

7  bit  0
---- ----  Byte 0
abcd efgh
|||| ||||
|||| |||+- 32768 Hz
|||| ||+-- 16384 Hz
|||| |+---  8192 Hz
|||| +----  4096 Hz
|||+------  2048 Hz
||+-------  1024 Hz
|+--------   512 Hz
+---------   256 Hz
7  bit  0
---- ----  Byte 1
abcd efgh
|||| ||||
|||| |||+-   128 Hz
|||| ||+--    64 Hz
|||| |+---    32 Hz
|||| +----    16 Hz
|||+------     8 Hz
||+-------     4 Hz
|+--------     2 Hz
+---------     1 Hz

Commands

Reset RTC ($10, $11)

Writing $10 or $11 to port $CA will send the "reset" command to the RTC. The S-3511A will then reset the year, month, day-of-month, day-of-week, hour, minute, second, config, and alarm registers. It is unknown if it resets the sub-second prescaler.

Write Configuration ($12)

Writing $12 to port $CA will send the "set configuration" command to the RTC. The 2003 expects that $CB contains valid contents by the time the 2003 sends that register's contents.

Read Configuration ($13)

Writing $13 to port $CA will send the "get configuration" command to the RTC.

Write current YMDdHMS ($14)

Writing $14 will set the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

Read current YMDdHMS ($15)

Writing $15 will get the current Year, Month, Day-of-Month, Day-of-Week, Hour, Minute, and Second.

Write current HMS ($16)

Writing $16 will set the current Hour, Minute, and Second.

These are the same as command $14.

Read current HMS ($17)

Writing $17 will get the current Hour, Minute, and Second.

Write alarm configuration ($18)

Writing $18 will set the current alarm configuration. The interpretation of these two bytes depend on the Configuration register

Nonsense alarm configuration ($19)

Writing $19 will set the current alarm configuration to $FFFF. The 2003 thinks it's reading from the S-3511A, but the S-3511A disagrees. $FFFF will be read back by the 2003.

Write nonsense ($1A)

Writing $1A expects to send 2 bytes to the RTC. The S-3511A ignores them.

Read nonsense ($1B)

Writing $1B expects to read 2 bytes from the RTC. The S-3511A leaves its output high, returning $FFFF.

Interrupts

The 2003 and S-3511A do not provide a thread-safe way to acknowledge the IRQ. Since the 2003 only holds one byte at a time, an interrupt can be fired in the middle of a multi-byte read or write without knowing what needs to be done for the rest of the command, nor how to safely restart that command when exiting the interrupt.

As such, the only choices are:

  • all communication to the 2003 happens while cartridge IRQs are disabled, or
  • the only thing the interrupt handler can do is mask the interrupt and then acknowledge it, and only afterwards handle any subsequent communication.