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| Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions. | | Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions. |
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| The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on.
| | == Format == |
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| == Architecture ==
| | The NEC V30MZ datasheet provides distinct names for opcodes, flags and registers, which the wiki refers to as ''NEC names''. As all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what is used throughout. For registers and flags, distinct NEC names are presented in the following format: Intel<sup>NEC</sup>. |
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| For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel<sup>NEC</sup>.
| | == Sections == |
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| === Registers ===
| | * [[NEC V30MZ registers]] |
| | | * [[NEC V30MZ flags]] |
| * Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers: | | * [[NEC V30MZ instruction set]] |
| ** '''AX'''<sup>AW</sup> ('''AL''', '''AH''') | | * [[NEC V30MZ interrupts]] |
| ** '''BX'''<sup>BW</sup> ('''BL''', '''BH''')
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| ** '''CX'''<sup>CW</sup> ('''CL''', '''CH''')
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| ** '''DX'''<sup>DW</sup> ('''DL''', '''DH''')
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| * Four additional 16-bit registers:
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| ** '''SI'''<sup>IX</sup>
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| ** '''DI'''<sup>IY</sup>
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| ** '''SP''' - stack pointer; the stack is always addressed in the stack segment (so as <code>SS:SP</code> far addresses).
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| ** '''BP'''
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| * Four segment registers:
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| ** '''CS'''<sup>PS</sup> - code segment,
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| ** '''DS'''<sup>DS0</sup> - data segment,
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| ** '''ES'''<sup>DS1</sup> - additional data segment,
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| ** '''SS''' - stack segment.
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| * '''IP'''<sup>PC</sup> - instruction pointer; instructions are always addressed in the code segment (so as <code>CS:IP</code> far addresses),
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| * '''FLAGS'''<sup>PSW</sup> - 16-bit processor flag register.
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| While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:
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| * '''AX''' benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
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| * '''CX''' is used for loop and repeat instructions as a counter.
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| * '''DX''' can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
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| * '''BX''', '''SI''', and '''DI''' can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
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| ** '''SI''' and '''DI''' are, in addition, used as source and destination pointers by string instructions.
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| * Similarly, '''BP''' can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.
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| === Flags ===
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| The V30MZ features the following flags:
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| 15 bit 8 7 bit 0
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| ---- ---- ---- ----
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| m111 odit sz0a 0p1c
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| | |||| || | | |
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| | |||| || | | +- Carry (CF<sup>CY</sup>)
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| | |||| || | +--- Parity (PF<sup>P</sup>)
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| | |||| || +------ Auxillary Carry (AF<sup>AC</sup>)
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| | |||| |+-------- Zero (Z)
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| | |||| +--------- Sign (S)
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| | |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>)
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| | ||+------------- Interrupt Enable (IF<sup>IE</sup>)
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| | |+-------------- Direction (DF<sup>DIR</sup>)
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| | +--------------- Overflow (OF<sup>V</sup>)
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| +-------------------- Mode (MD)
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| In general, they are set by operations as follows:
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| * '''Carry''' - stores the carry/borrow state of the last arithmetic operation, or the bit shifted to it for shift/rotate operations. | |
| * '''Parity''' - set to <tt>1</tt> if, after arithmetic and logical operations, the lower 8 bits of the result are even.
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| * '''Auxillary Carry''' - stores the carry state from the lower 4-bit nibble (bits 0-3) to the higher 4-bit nibble (bits 4-7), or the borrow state from the higher nibble to the lower nibble.
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| * '''Zero''' - set to <tt>1</tt> if, after arithmetic and logical operations, the result is equal to zero.
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| * '''Sign''' - set to <tt>1</tt> if, after arithmetic and logical operations, the highest bit of the result is set.
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| * '''Overflow''' - set to <tt>1</tt> if an overflow occured as part of the arithmetic operation.
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| There are also programmer-controlled control flags:
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| * '''Single Step''' - if set to <tt>1</tt>, after every instruction, a software interrupt (vector 1) is generated.
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| * '''Interrupt Enable''' - if set to <tt>1</tt>, enables maskable interrupt handling via the interrupt vector table; cleared to <tt>0</tt> as part of interrupt handling and restored by the <tt>IRET</tt> opcode.
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| * '''Direction''' - if set to <tt>1</tt>, string instructions decrement pointers as part of their operation; if set to <tt>0</tt>, the pointers are to be incremented. | |
| * '''Mode''' - used for 8080 emulation mode in other V20/V30-family chips, does nothing on V30MZ
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| == Instruction set ==
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| {| class="wikitable sortable"
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| |+ V30MZ Instruction Set
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| |-
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| ! Instruction
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| ! Opcode (hex)
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| ! Opcode (bin)
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| ! Bytes
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| ! Cycles
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| ! Flags
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| ! NEC mnemonic
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| ! Notes
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| |-
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| | <tt>ADD AL, imm8</tt>
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| | <tt>04</tt>
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| | <tt>00000100</tt>
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| | 2
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| | 1
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| | <tt>O...SZAPC</tt>
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| | <tt>ADD AL, imm8</tt>
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| |-
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| | <tt>ADD AX, imm16</tt>
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| | <tt>05</tt>
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| | <tt>00000101</tt>
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| | 3
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| | 1
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| | <tt>O...SZAPC</tt>
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| | <tt>ADD AW, imm16</tt>
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| |-
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| | <tt>ADD mem8, imm8</tt>
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| | <tt>80 rm</tt> / <tt>82 rm</tt>
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| | <tt>100000.0 oo000mm</tt>
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| | 3-5
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| | 3
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| | <tt>O...SZAPC</tt>
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| | <tt>ADD mem8, imm8</tt>
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| |-
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| |}
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| == Links == | | == Links == |
