Memory map
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The WonderSwan's SoC enforces the following memory map layout:
| Bus | Address range | Access width | Access speed | Read/Write | |
|---|---|---|---|---|---|
| Internal | 0x00000 0x0FFFF |
16-bit | 1 cycle | RW | |
| Cartridge | 0x10000 0xFFFFF |
0x10000 0x1FFFF |
8-bit | ??? | RW |
| 0x20000 0xFFFFF |
8/16-bit (configurable) | 1/3 cycles (configurable) | R | ||
Internal
The WonderSwan SoC features an unified memory architecture; that is, the CPU, Display and Sound components can access the RAM in time divisions of the chip's clock. This allows for a mostly stall-free development experience.
However, a few elements of the memory live at fixed locations.
| Address | WonderSwan | WonderSwan Color (2BPP mode) | WonderSwan Color (4BPP mode) |
|---|---|---|---|
| 0x0000 | Interrupt vectors (256 x 32-bit segment:offset address) | ||
| 0x0400 | Free RAM | ||
| 0x2000 | Tile data (bank 0) | Free RAM | |
| 0x4000 | Tile data (bank 1) | Tile data (bank 0) | |
| 0x6000 | Free RAM | ||
| 0x8000 | Tile data (bank 1) | ||
| 0xC000 | Free RAM | ||
| 0xFE00 | Color palette | ||
| 0xFFFF | |||
In addition, some elements can be placed at configurable locations in RAM, but with restrictions:
| Type | Lowest address | Highest address | Alignment |
|---|---|---|---|
| Screen | 0x0000 | 0x3800 0x7800(color) |
0x800 (2048) bytes |
| Sprite table | 0x0000 | 0x3E00 0x7E00(color) |
0x200 (512) bytes |
| Sound wave table | 0x0000 | 0x3FC0 | 0x40 (64) bytes |
Cartridge
The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a Mapper. There exists a standard layout common to all official mappers:
| Address range | Bank |
|---|---|
| 0x10000 0x1FFFF |
SRAM (or flashable ROM) |
| 0x20000 0x2FFFF |
ROM bank 0 |
| 0x30000 0x3FFFF |
ROM bank 1 |
| 0x40000 0xFFFFF |
ROM linear (EX) bank |
