NEC V30MZ

The NEC V30MZ is the CPU component of the WonderSwan SoC.

Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.

The NEC V30MZ datasheet uses distinct names for opcodes and registers (NEC names); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (Intel names), the latter is what the wiki - and most community tooling - has standardized on.

Architecture

For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel^NEC.

Registers

• Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
  • AX^AW (AL, AH)
  • BX^BW (BL, BH)
  • CX^CW (CL, CH)
  • DX^DW (DL, DH)
• Four additional 16-bit registers:
  • SI^IX
  • DI^IY
  • SP
  • BP
• Four segment registers:
  • CS^PS - code segment,
  • DS^DS0 - data segment,
  • ES^DS1 - additional data segment,
  • SS - stack segment.
• IP^PC - instruction pointer; instructions are always addressed in the code segment (so as CS:IP far addresses),
• FLAGS^PSW - 16-bit processor flag register.

Flags

15  bit  8  7  bit  0
 ---- ----  ---- ----
 m111 odit  sz0a 0p1c
 |    ||||  || |  | |
 |    ||||  || |  | +- Carry (CF<sup>CY</sup>)
 |    ||||  || |  +--- Parity (PF<sup>P</sup>)
 |    ||||  || +------ Auxillary Carry (AF<sup>AC</sup>)
 |    ||||  |+-------- Zero (Z)
 |    ||||  +--------- Sign (S)
 |    |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>)
 |    ||+------------- Interrupt Enable (IF<sup>IE</sup>)
 |    |+-------------- Direction (DF<sup>DIR</sup>)
 |    +--------------- Overflow (OF<sup>V</sup>)
 +-------------------- Mode (MD)

Links

• NEC V30MZ datasheet
• STSWS - CPU - V30MZ/V Series Microprocessor