EEPROM
The WonderSwan utilizes M93LCx6-compatible EEPROMs:
- in the SoC:
- 1 Kbit internal EEPROM (M93LC46-compatible) on the WonderSwan,
- 16 Kbit internal EEPROM (M93LC86-compatible) on the WonderSwan Color,
- on cartridges:
- 1 Kbit cartridge EEPROM (M93LC46-compatible)
- 8 Kbit cartridge EEPROM (M93LC76-compatible)
- 16 Kbit cartridge EEPROM (M93LC86-compatible)
Additional variants exists which were not seen on any production cartridge:
- 256 bit EEPROM (M93LC06-compatible)
- 2 Kbit EEPROM (M93LC56-compatible)
- 4 Kbit EEPROM (M93LC66-compatible)
Commands
READ - Read Word
The READ command takes an address of a word (address 0 => bytes 0, 1; address 1 => bytes 2, 3; ...) and returns the word at that address.
WRITE - Write Word
The WRITE command takes an address of a word (address 0 => bytes 0, 1; address 1 => bytes 2, 3; ...) and the word to write to it, then writes the word.
ERASE - Erase Word
The ERASE command takes an address of a word (address 0 => bytes 0, 1; address 1 => bytes 2, 3; ...) and erases the word at that address, setting it to 0xFFFF.
WDS - Write Disable
TODO
WRAL - Write All
This command is not guaranteed to be present on all EEPROMs.
TODO
ERAL - Erase All
This command is not guaranteed to be present on all EEPROMs.
TODO
WEN - Write Enable
TODO
I/O ports
The I/O ports listed refer to the internal EEPROM; for the cartridge EEPROM port numbers, refer to the mapper documentation.
It is recommended to only access the data and command ports with aligned word reads/writes; see the Errata section for more information.
Internal EEPROM Data ($BA, $BB)
15 bit 8 7 bit 0 ---- ---- ---- ---- dddd dddd dddd dddd |||| |||| |||| |||| ++++-++++--++++-++++- Data read from/written to the EEPROM.
This port functions as a shared buffer for both "read" and "write" modes. (TODO: Verify)
Internal EEPROM Command ($BC, $BD)
Command Pattern 1
15 bit 8 7 bit 0
---- ---- ---- ----
0000 0001 ooaa aaaa (¼, 1 Kbit - M93LC06/46)
0000 01oo aaaa aaaa (2, 4 Kbit - M93LC56/66)
0001 ooaa aaaa aaaa (8, 16 Kbit - M93LC76/86)
|||| |||| ||||
||++--++++-++++- Address (MSb .. LSb)
++-------------- Opcode:
01 - WRITE
10 - READ
11 - ERASE
Command Pattern 2
15 bit 8 7 bit 0
---- ---- ---- ----
0000 0001 00ss .... (¼, 1 Kbit - M93LC06/46)
0000 0100 ss.. .... (2, 4 Kbit - M93LC56/66)
0001 00ss .... .... (8, 16 Kbit - M93LC76/86)
||
++------------ Sub-Opcode:
00 - WDS
01 - WRAL
01 - ERAL
11 - WEN
The value written to this port can be read back; it is not affected by EEPROM Control.
Internal EEPROM Control ($BE, $BF write)
15 bit 8 7 bit 0
---- ---- ---- ----
.... .... PSWR ....
||||
|||+------ Read mode: 1 for READ command, 0 otherwise
||+------- Write mode: 1 for WRITE and WRAL command, 0 otherwise
|+-------- Short mode: 1 for ERASE, WDS, ERAL and WEN command, 0 otherwise
+--------- 1 to enable internal EEPROM write protection.
Cannot be cleared once set.
The mode flags control the behaviour of the EEPROM interface:
- Read mode: Sends 16 bits from Command, then reads 16 bits to Data.
- Write mode: Sends 16 bits from Command, then 16 bits from Data. De-asserts Microwire chip select, then re-asserts it and waits for the EEPROM to confirm command completion.
- Short mode: Sends 16 bits from Command, de-asserts Microwire chip select.
Also note that nothing inside the SoC or 2001 checks that the contents of the command register matches the bit set in this register.
Internal EEPROM Status ($BE, $BF read)
15 bit 8 7 bit 0
---- ---- ---- ----
.... .... p... ..rd
| ||
| |+- 0 after a Read command is initiated,
| | 1 once a Read command is completed.
| | Unaffected by Write/Erase commands.
| +-- 0 if the EEPROM is busy,
| 1 if a command can be accepted (idle).
+--------- Internal EEPROM write protection:
0 = disabled, 1 = enabled
Internal EEPROM Layout
| Offset | Length | Contents |
|---|---|---|
| $00 | 96 | Program data. Can be written by programs even if write protection has been enabled. |
| $60 | 16 | Owner name, custom character set. |
| $70 | 1 | Owner birthday year, BCD, first/higher two digits |
| $71 | 1 | Owner birthday year, BCD, last/lower two digits |
| $72 | 1 | Owner birthday month, BCD |
| $73 | 1 | Owner birthday day, BCD |
| $74 | 1 | Owner gender: 0 - ? |
| $75 | 1 | Owner blood type: 0 - ? |
| $76 | 1 | Last booted cartridge developer/publisher ID |
| $77 | 1 | Last booted cartridge game ID |
| $78 | 1 | Last booted cartridge game version |
| $7C | 1 | Stored cartridge ID/version change counter |
| $7D | 1 | Owner name change counter |
| $7E | 2 | System startup counter |
| $83 | 1 | Color console configuration |
| $84 | ? | Custom splash animation, if present |
Owner name character set
.0
|
.1
|
.2
|
.3
|
.4
|
.5
|
.6
|
.7
|
.8
|
.9
|
.A
|
.B
|
.C
|
.D
|
.E
|
.F
| |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0.
|
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | |
1.
|
F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U |
2.
|
V | W | X | Y | Z | ♥ | ♪ | + | - | ? | . |
Color console configuration
7 bit 0 ---- ---- sc.. ..vv || || || ++- Volume level |+-------- Contrast (WSC): 0 = Low, 1 = High +--------- Custom splash animation enabled
Hardware notes
EEPROM command bits are shifted out starting from the most significant bit of the port.
+----> EEPROM Serial Data
|
[0] <= [0000 0001 ooaa aaaa]
EEPROM Command Port
While the M93LCx6 family supports byte organization, the WonderSwan always uses word organization. As such, this implementation detail is omitted in this documentation.
Errata
Non-word access on ASWAN
On the ASWAN SoC, accessing the internal EEPROM command ports as bytes only works correctly for even addresses. For odd addresses, these accesses return open bus; this means that unaligned word accesses also don't work, as they are converted to one odd and one even byte access internally.
It is recommended to only use aligned word port accesses to talk to the internal EEPROM.
This issue is not present on the SPHINX and newer SoCs, including in "mono" emulation mode, as well as the cartridge bus (which is always forced to be accessed per byte).
