Interrupts
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The WonderSwan features fourteen different interrupts:
- CPU interrupts - six provided by the V30MZ CPU ($00-$05),
- Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset
V):- Level - will be reissued so long as the prerequisite condition is raised or the interrupt is disabled,
- Edge - will only be issued once; acknowledging the interrupt prevents reissuing until the condition is toggled again.
The user can additionally define and use any of the 256 interrupt vectors in their own code.
| Source | Type | Index | Description |
|---|---|---|---|
| CPU | N/A | $00 | DIV or IDIV instruction divide error (division by zero or result overflow) |
| $01 | Single-step (T flag) | ||
| $02 | NMI (non-maskable interrupt) | ||
| $03 | INT 3 opcode | ||
| $04 | INTO opcode (if V = 1) | ||
| $05 | BOUND opcode (if index out of bounds) | ||
| Hardware | Level | V + 0 | UART Send Ready |
| Edge | V + 1 | Key Pressed | |
| Level | V + 2 | Cartridge IRQ | |
| V + 3 | UART Receive Ready | ||
| Edge | V + 4 | Display Interrupt Line Match | |
| V + 5 | Vertical Blank Timer | ||
| V + 6 | Display Vertical Blank | ||
| V + 7 | Horizontal Blank Timer |
I/O Ports
Interrupt Vector
7 bit 0
---- ----
VVVV V...
|||| ||||
++++-++++- Interrupt vector offset
(lowest three bits ignored)
Interrupt Enable
7 bit 0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
(acts as a mask)
Interrupt Status
7 bit 0 ---- ---- iiii iiii |||| |||| ++++-++++- 1 if interrupt requested
Interrupt Acknowledge
7 bit 0 ---- ---- iiii iiii |||| |||| ++++-++++- Write 1 to clear interrupt request
Interrupt NMI Control
7 bit 0 ---- ---- ...b .... +----- Enable NMI on low battery detection
