DMA

The WonderSwan Color introduced two DMA blocks:

• General DMA (GDMA) - allowing for fast IRAM/ROM -> IRAM transfers,
• Sound DMA (SDMA) - allowing for IRAM/ROM -> sound transfers in a much less CPU-intensive way than an interrupt.

General DMA

GDMA Source Address ($40, $41, $42)

23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)

DMA allows source addresses in IRAM and ROM; any attempt to access SRAM causes DMA to immediately return, even if in the middle of a transfer.

TODO: What about source addresses in ROM configured as 8-bit?

GDMA Destination Address ($44, $45)

15  bit  8  7  bit  0
 ---- ----  ---- ----
 aaaa aaaa  aaaa aaaa
 ++++-++++--++++-++++- Destination address in IRAM

GDMA allows destination addresses in IRAM.

GDMA Length ($46, $47)

15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes

GDMA Control ($48)

7  bit  0
---- ----
ed.. ....
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on

The CPU is stalled immediately after General DMA is enabled. General DMA takes (5 + 2 * length) cycles to complete.

Sound DMA

Sound DMA is a specialized form of General DMA with a hard-coded destination and built-in timer logic. As such, all of the rules for GDMA apply to SDMA as well.

Due to its need to access the external cartridge bus, Sound DMA steals 7 cycles - the same amount of time GDMA would take for transferring one byte - every 128 cycles. These are always cycles {117, 118, 119, 120, 121, 122, 123} mod 128.

TODO: How does Sound DMA interact with the cartridge waitstate configuration?

SDMA Source Address ($4A, $4B, $4C)

23  bit 16 15  bit  8  7  bit  0
 ---- ----  ---- ----  ---- ----
 .... hhhh  llll llll  llll llll
      ++++--++++-++++--++++-++++- Linear source address
                                  ($00000 - $FFFFF)

SDMA Length ($4E, $4F)

15  bit  8  7  bit  0
 ---- ----  ---- ----
 bbbb bbbb  bbbb bbbb
 ++++-++++--++++-++++- Transfer length, in bytes

SDMA Control ($50)

7  bit  0
---- ----
ed.t r?ff
|| | | ++- Frequency/Rate:
|| | |       0 = 24000/1 = 24000 Hz
|| | |       1 = 24000/2 = 12000 Hz
|| | |       2 = 24000/4 =  6000 Hz
|| | |       3 = 24000/6 =  4000 Hz
|| | +---- Repeat: 0 = one-shot, 1 = auto-repeat
|| +------ Target:
||           0 = Channel 2 (port $89)
||           1 = Hyper Voice
|+-------- Direction: 0 = increment, 1 = decrement
+--------- Enable DMA: 0 = off, 1 = on

The CPU is stalled immediately after General DMA is enabled. General DMA takes (5 + 2 * length) cycles to complete.