Cartridge connector

Memory access

Both the ROM and the SRAM chip use a standard asynchronous memory interface.

It is presumed that:

• the CPU sets the address lines after the rising edge of /OE while /OE is high,
• the CPU sets the data lines after the falling edge of /OE, while /OE is low (TODO: only confirmed for I/O writes),
• the CPU latches the data lines on the subsequent rising edge of /OE.

Memory may be accessed in 8-bit or 16-bit mode. SRAM reads/writes always happen in 8-bit mode, while ROM reads/writes can happen in 8-bit or 16-bit mode depending on header configuration.

Note that in 16-bit mode, the output on address line A0 is undetermined and should be ignored.

Pinout

Cartridge              Console
(label side)            (back)
____________
       |====|
____   |--01| -- GND
... \  | -02| <- CPU A15
... |  | -03| <- CPU A10
... |  | -04| <- CPU A11
... |  | -05| <- CPU A9
... |  | -06| <- CPU A8
... |  | -07| <- CPU A13
... |  | -08| <- CPU A14
... |  | -09| <- CPU A12
... |  | -10| <- CPU A7
... |  | -11| <- CPU A6
... |  | -12| <- CPU A5
... |  | -13| <- CPU A4
... |  | -14| <> D15
... |  | -15| <> D14
... |  | -16| <> D7
... |  | -17| <> D6
... |  | -18| <> D5
... |  | -19| <> D4
... |  | -20| <> D3
... |  | -21| <> D2
... |  | -22| <> D1
... |  | -23| <> D0
... |  |--24| -- +3.3V
... |  |--25| -- +3.3V
... |  | -26| <- CPU A0
... |  | -27| <- CPU A1
... |  | -28| <- CPU A2
... |  | -29| <- CPU A3
... |  | -30| <- CPU A19
... |  | -31| <- CPU A18
... |  | -32| <- CPU A17
... |  | -33| <- CPU A16
... |  | -34| <> D8
... |  | -35| <> D9
... |  | -36| <> D10
... |  | -37| <> D11
... |  | -38| <> D12
... |  | -39| <> D13
... |  | -40| <- /RESET
... |  | -41| -> /MBC
... |  | -42| <- M/IO (Memory/IO)
... |  | -43| <- /RD  (Read enable)
... |  | -44| <- /WR  (Write enable)
... |  | -45| <- /SEL (Cartridge select)
... |  | -46| -> /IRQ (Interrupt request)
____/  | -47| <- CLK
       |--48| -- GND
_______|====|

Cartridge              Console
(label side)            (back)

Mechanical details

Distance	Length (in mm)
Distance pad to pad	1.25
Left edge to first pad	0.7
Last pad to right edge	0.95
Bottom edge to longer pads (GND, Vcc)	0.5
Bottom edge to shorter pads	1

Signal descriptions

• /RESET: Reset signal output from the console. On a mono WonderSwan, it stays low for about 18 milliseconds after power-up.
• /MBC: Authentication handshake signal. A cartridge is required to communicate over this pin shortly after reset.
• M/IO: Memory/IO bus selection. The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF):
  • When Memory/IO is high, pins A0-A19 specify the 20-bit linear memory address.
  • When Memory/IO is low, pins A0-A7 specify the 8-bit I/O port address, pins A8-A15 are low, pins A16-A19 are a copy of the I/O port address bits 4-7.
• /IRQ: Cartridge interrupt. When this pin is pulled low, the console will trigger a maskable cartridge interrupt.
• CLK: A clock provided by the console. This pin outputs a frequency of 384 KHz, derived from the 12.288 MHz system clock; on the WonderSwan Color, it can optionally be configured by software to provide a 6.144 MHz frequency instead.

Timing requirements

The /OE or /WE signal appear to have a frequency of about 3.072 MHz, derived from the 12.288 MHz system clock. This leaves half this period, so about 162 ns, to handle one memory access.

TODO: Verify how using ROM/SRAM wait states affects this.

Authentication handshake

Shortly after /RESET goes high, a handshake between the SoC and the cartridge is performed, in order:

• /MBC is held high.
• On the rising edge of CLK, A0-A3 are set to 0x5 and A16-A19 are set to 0xA.
• The cartridge continues to hold /MBC high for three additional CLK rising edges. Note that the SoC appears to allow some variance in this number of cycles.
• For each subsequent rising edge of CLK, the cartridge is expected to output the following binary sequence through its /MBC pin: 1000101000101000000111.
• After this is finished, /MBC is expected to stay high indefinitely.

On a successful handshake, the SoC sets bit 7 of the System Control I/O port. The boot ROM will refuse to boot the cartridge if this bit is not set; on the WonderSwan Color, it will refuse to start the system at all.

An example public domain (CC0) VHDL implementation by trap15 is available here.