NEC V30MZ: Difference between revisions
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=== Flags === | === Flags === | ||
15 bit 8 7 bit 0 | |||
15 bit 8 7 bit 0 | ---- ---- ---- ---- | ||
m111 odit sz0a 0p1c | |||
| |||| || | | | | |||
| |||| || | | +- Carry (CF<sup>CY</sup>) | |||
| |||| || | +--- Parity (PF<sup>P</sup>) | |||
| |||| || +------ Auxillary Carry (AF<sup>AC</sup>) | |||
| |||| |+-------- Zero (Z) | |||
| |||| +--------- Sign (S) | |||
| |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>) | |||
| ||+------------- Interrupt Enable (IF<sup>IE</sup>) | |||
| |+-------------- Direction (DF<sup>DIR</sup>) | |||
| +--------------- Overflow (OF<sup>V</sup>) | |||
+-------------------- Mode (MD) | |||
== Instruction set == | == Instruction set == | ||
| Line 101: | Line 97: | ||
|- | |- | ||
|} | |} | ||
== Links == | == Links == | ||
Revision as of 19:01, 2 August 2024
The NEC V30MZ is the CPU component of the WonderSwan SoC.
Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.
The NEC V30MZ datasheet uses distinct names for opcodes and registers (NEC names); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (Intel names), the latter is what the wiki - and most community tooling - has standardized on.
Architecture
For this section, elements of the architecture which have distinct NEC names are provided in the following format: IntelNEC.
Registers
- Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
- AXAW (AL, AH)
- BXBW (BL, BH)
- CXCW (CL, CH)
- DXDW (DL, DH)
- Four additional 16-bit registers:
- SIIX
- DIIY
- SP - stack pointer; the stack is always addressed in the stack segment (so as
SS:SPfar addresses). - BP
- Four segment registers:
- CSPS - code segment,
- DSDS0 - data segment,
- ESDS1 - additional data segment,
- SS - stack segment.
- IPPC - instruction pointer; instructions are always addressed in the code segment (so as
CS:IPfar addresses), - FLAGSPSW - 16-bit processor flag register.
While the eight registers can be used in a general-purpose manner, some opcodes are constrained to only using certain registers:
- AX benefits from more compact encoding for certain instructions; it's also used as an output and input register in multiplication/division, port access, BCD conversions, and (as AL) in the XCHG opcode.
- CX is used for loop and repeat instructions as a counter.
- DX can be used used as the address register for port access, it is also used as an output register for word multiplication/division.
- BX, SI, and DI can be used as indices for accessing data in tables in the DS segment (or other segments when overridden).
- SI and DI are, in addition, used as source and destination pointers by string instructions.
- Similarly, BP can be used as an index for accessing stack data; this makes it particularly useful as a frame pointer.
Flags
15 bit 8 7 bit 0 ---- ---- ---- ---- m111 odit sz0a 0p1c | |||| || | | | | |||| || | | +- Carry (CFCY) | |||| || | +--- Parity (PFP) | |||| || +------ Auxillary Carry (AFAC) | |||| |+-------- Zero (Z) | |||| +--------- Sign (S) | |||+------------ Single StepBreak (TFBRK) | ||+------------- Interrupt Enable (IFIE) | |+-------------- Direction (DFDIR) | +--------------- Overflow (OFV) +-------------------- Mode (MD)
Instruction set
| Instruction | Opcode (hex) | Opcode (bin) | Bytes | Cycles | Flags | NEC mnemonic | Notes |
|---|---|---|---|---|---|---|---|
| ADD AL, imm8 | 04 | 00000100 | 2 | 1 | O...SZAPC | ADD AL, imm8 | |
| ADD AX, imm16 | 05 | 00000101 | 3 | 1 | O...SZAPC | ADD AW, imm16 | |
| ADD mem8, imm8 | 80 rm / 82 rm | 100000.0 oo000mm | 3-5 | 3 | O...SZAPC | ADD mem8, imm8 |
