Bandai 2001: Difference between revisions
m (if I say $C8 is byte-wide, only talk about 8 bits) |
m (merge cells) |
||
| Line 23: | Line 23: | ||
| Command and address | | Command and address | ||
|- | |- | ||
! $C8 | ! rowspan=2|$C8 | ||
| External EEPROM Command | | External EEPROM Command | ||
| style="text-align: right" | <tt style="white-space: nowrap">ACWR ....</tt> | | style="text-align: right" | <tt style="white-space: nowrap">ACWR ....</tt> | ||
| Line 29: | Line 29: | ||
| Abort (A), Command (C), Write (W), Read (R) | | Abort (A), Command (C), Write (W), Read (R) | ||
|- | |- | ||
| External EEPROM Status | | External EEPROM Status | ||
| style="text-align: right" | <tt style="white-space: nowrap">.... ..rd</tt> | | style="text-align: right" | <tt style="white-space: nowrap">.... ..rd</tt> | ||
Revision as of 21:49, 19 August 2023
In addition to the normal Cartridge banking interface, Bandai's 2001 adds three registers for interacting with a Microwire EEPROM:
| Category | Port | Description | Bits | Type | Notes |
|---|---|---|---|---|---|
| External EEPROM | $C4 | External EEPROM Data | dddd dddd dddd dddd | RW16 | Data (d) |
| $C6 | External EEPROM Command | 0001 CCaa aaaa aaaa
or 0000 0001 CCaa aaaa |
RW16 | Command and address | |
| $C8 | External EEPROM Command | ACWR .... | W8 | Abort (A), Command (C), Write (W), Read (R) | |
| External EEPROM Status | .... ..rd | R8 | Ready (r), Done (d) |
The specific meaning of the "Command" register depends on the model of EEPROM on the PCB. Only three Microwire EEPROMs have been seen used (equivalent to 93C46, 93C76, and 93C86)
On the 2001, the EEPROM "done" bit is buggy and doesn't have useful information. It's set when a Read completes, but is only cleared when a Command or Write is started. (To be useful it would need to also be cleared when a Read is started).
If more than ACWR bit is set at the same time, the 2001 ignores it.
The CWR bits specify how many data bits are sent/received. C: No data bits. W: Send Data register after command register. R: Receive data register after sending command register.
If the A bit is set, the transaction immediately stops.
(Upload logic analyzer traces here)
