NEC V30MZ: Difference between revisions
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Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions. | Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions. | ||
The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki has standardized on. | The NEC V30MZ datasheet uses distinct names for opcodes and registers (''NEC names''); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (''Intel names''), the latter is what the wiki - and most community tooling - has standardized on. | ||
== | == Architecture == | ||
* | For this section, elements of the architecture which have distinct NEC names are provided in the following format: Intel<sup>NEC</sup>. | ||
=== Registers === | |||
* Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers: | |||
** '''AX'''<sup>AW</sup> ('''AL''', '''AH''') | |||
** '''BX'''<sup>BW</sup> ('''BL''', '''BH''') | |||
** '''CX'''<sup>CW</sup> ('''CL''', '''CH''') | |||
** '''DX'''<sup>DW</sup> ('''DL''', '''DH''') | |||
* Four additional 16-bit registers: | |||
** '''SI'''<sup>IX</sup> | |||
** '''DI'''<sup>IY</sup> | |||
** '''SP''' | |||
** '''BP''' | |||
* Four segment registers: | |||
** '''CS'''<sup>PS</sup> - code segment, | |||
** '''DS'''<sup>DS0</sup> - data segment, | |||
** '''ES'''<sup>DS1</sup> - additional data segment, | |||
** '''SS''' - stack segment. | |||
* '''IP'''<sup>PC</sup> - instruction pointer; instructions are always addressed in the code segment (so as <code>CS:IP</code> far addresses), | |||
* '''FLAGS'''<sup>PSW</sup> - 16-bit processor flag register. | |||
=== Flags === | |||
<pre> | |||
15 bit 8 7 bit 0 | |||
---- ---- ---- ---- | |||
m111 odit sz0a 0p1c | |||
| |||| || | | | | |||
| |||| || | | +- Carry (CF<sup>CY</sup>) | |||
| |||| || | +--- Parity (PF<sup>P</sup>) | |||
| |||| || +------ Auxillary Carry (AF<sup>AC</sup>) | |||
| |||| |+-------- Zero (Z) | |||
| |||| +--------- Sign (S) | |||
| |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>) | |||
| ||+------------- Interrupt Enable (IF<sup>IE</sup>) | |||
| |+-------------- Direction (DF<sup>DIR</sup>) | |||
| +--------------- Overflow (OF<sup>V</sup>) | |||
+-------------------- Mode (MD) | |||
</pre> | |||
<!-- | |||
== Instruction set == | |||
{| class="wikitable sortable" | |||
|+ V30MZ Instruction Set | |||
|- | |||
! Instruction | |||
! Opcode (hex) | |||
! Opcode (bin) | |||
! Bytes | |||
! Cycles | |||
! Flags | |||
! NEC mnemonic | |||
! Notes | |||
|- | |||
| <tt>ADD AL, imm8</tt> | |||
| <tt>04</tt> | |||
| <tt>00000100</tt> | |||
| 2 | |||
| 1 | |||
| <tt>O...SZAPC</tt> | |||
| <tt>ADD AL, imm8</tt> | |||
| | |||
|- | |||
| <tt>ADD AX, imm16</tt> | |||
| <tt>05</tt> | |||
| <tt>00000101</tt> | |||
| 3 | |||
| 1 | |||
| <tt>O...SZAPC</tt> | |||
| <tt>ADD AW, imm16</tt> | |||
| | |||
|- | |||
| <tt>ADD mem8, imm8</tt> | |||
| <tt>80 rm</tt> / <tt>82 rm</tt> | |||
| <tt>100000.0 oo000mm</tt> | |||
| 3-5 | |||
| 3 | |||
| <tt>O...SZAPC</tt> | |||
| <tt>ADD mem8, imm8</tt> | |||
| | |||
|- | |||
|} | |||
--> | |||
== Links == | == Links == | ||
Revision as of 18:18, 2 August 2024
The NEC V30MZ is the CPU component of the WonderSwan SoC.
Unlike the NEC V20/V30 CPU family, the V30MZ is fully compatible with the Intel 80186's documented behaviour, as well as some of its undocumented behaviour (such as the SALC opcode); it also omits the V20/V30's opcode extensions.
The NEC V30MZ datasheet uses distinct names for opcodes and registers (NEC names); as all homebrew compilers and assemblers for the platform utilize Intel's official naming (Intel names), the latter is what the wiki - and most community tooling - has standardized on.
Architecture
For this section, elements of the architecture which have distinct NEC names are provided in the following format: IntelNEC.
Registers
- Four 16-bit general-purpose registers, with their (low, high) components accessible as individual 8-bit sub-registers:
- AXAW (AL, AH)
- BXBW (BL, BH)
- CXCW (CL, CH)
- DXDW (DL, DH)
- Four additional 16-bit registers:
- SIIX
- DIIY
- SP
- BP
- Four segment registers:
- CSPS - code segment,
- DSDS0 - data segment,
- ESDS1 - additional data segment,
- SS - stack segment.
- IPPC - instruction pointer; instructions are always addressed in the code segment (so as
CS:IPfar addresses), - FLAGSPSW - 16-bit processor flag register.
Flags
15 bit 8 7 bit 0 ---- ---- ---- ---- m111 odit sz0a 0p1c | |||| || | | | | |||| || | | +- Carry (CF<sup>CY</sup>) | |||| || | +--- Parity (PF<sup>P</sup>) | |||| || +------ Auxillary Carry (AF<sup>AC</sup>) | |||| |+-------- Zero (Z) | |||| +--------- Sign (S) | |||+------------ Single Step<sup>Break</sup> (TF<sup>BRK</sup>) | ||+------------- Interrupt Enable (IF<sup>IE</sup>) | |+-------------- Direction (DF<sup>DIR</sup>) | +--------------- Overflow (OF<sup>V</sup>) +-------------------- Mode (MD)
