Cartridge: Difference between revisions
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(Created page with "== Cartridge bus == The cartridge bus allows both memory access (to linear addresses 0x10000-0xFFFFF) and I/O access (to ports 0xC0-0xFF). To facilitate this, the Memory/IO pin is used: * When Memory/IO is asserted '''high''', all bus address pins specify the 20-bit linear memory address. * When Memory/IO is asserted '''low''', bus address pins 0-7 specify the port address bits 0-7, bus address pins 8-15 are low, bus address pins 16-19 specify the port address bits 4-...") |
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== Cartridge bus == | == Cartridge bus == | ||
The cartridge bus | The SoC forwards some memory and I/O accesses to the cartridge bus: | ||
* memory: physical addresses 0x10000 - 0xFFFFF, | |||
* I/O: ports 0xC0 - 0xFF. | |||
To facilitate this, the Memory/IO pin is used: | To facilitate this, the Memory/IO pin is used: | ||
Latest revision as of 16:58, 2 August 2024
Cartridge bus
The SoC forwards some memory and I/O accesses to the cartridge bus:
- memory: physical addresses 0x10000 - 0xFFFFF,
- I/O: ports 0xC0 - 0xFF.
To facilitate this, the Memory/IO pin is used:
- When Memory/IO is asserted high, all bus address pins specify the 20-bit linear memory address.
- When Memory/IO is asserted low, bus address pins 0-7 specify the port address bits 0-7, bus address pins 8-15 are low, bus address pins 16-19 specify the port address bits 4-7.
Interrupts
The cartridge bus provides an /IRQ pin which can be used by the cartridge to assert an interrupt.
