SoC: Difference between revisions
(2 intermediate revisions by the same user not shown) | |||
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7 bit 0 | 7 bit 0 | ||
---- ---- | ---- ---- | ||
c4C. i | c4C. i.sl | ||
||| | || | ||| | || | ||
||| | |+- Cartridge clock speed? | ||| | |+- Cartridge clock speed? | ||
Line 53: | Line 53: | ||
S... ...p | S... ...p | ||
| | | | | | ||
| +- 1 = | | +- 1 = Request power off | ||
+--------- 0 = WonderSwan Color (SPHINX) | +--------- 0 = WonderSwan Color (SPHINX) | ||
1 = SwanCrystal (SPHINX2) | 1 = SwanCrystal (SPHINX2) | ||
</pre> | </pre> | ||
After setting the "request power off" bit to 1, halting the CPU will cause the console to shut down. | |||
TODO: <tt>$AC</tt> bit 0 seems to also shut down the console. | |||
{{Anchor|System Test}} | |||
=== System Test ($A3) === | |||
Note that this port is only writable as a byte - writing a word to <tt>$A2</tt> does not write to this byte. | |||
<pre> | |||
7 bit 0 | |||
---- ---- | |||
.... u?vh | |||
| |+- Enable HBlank Timer test | |||
| +-- Enable VBlank Timer test | |||
+---- Enable UART test | |||
</pre> | |||
The timer tests ignore the reload value and clock the timers at 3072000? Hz. The enable bit is still respected. | |||
The UART test disables the 9600/38400 baud clock divider, instead operating the EXT port's UART lines at 192000 baud. | |||
== Notes == | == Notes == | ||
<references /> | <references /> |
Latest revision as of 15:53, 9 April 2025
The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.
There exist three variants of the SoC:
- ASWAN, used in the WonderSwan,
- SPHINX, used in the WonderSwan Color,
- SPHINX2, used in the SwanCrystal.
A fourth variant, CAIRO, was planned[1]. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but is not known to have been licensed for any commercial product.
I/O ports
System Control ($A0)
7 bit 0 ---- ---- C??? swcl | |||| | |||+- Boot ROM lockout: 0 = off, 1 = on | ||+-- Color model: 0 = no, 1 = yes | |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit | +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +1 +--------- Cartridge bus test OK
System Control 2 ($60, color)
7 bit 0 ---- ---- c4C. i.sl ||| | || ||| | |+- Cartridge clock speed? ||| | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1 ||| +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1 ||+------- 1 = 4bpp "chunky"; requires all previous |+-------- 1 = 4bpp; requires all previous +--------- 0 = mono, 1 = color; also controls access to WSC-specific features (extra RAM, DMA, etc.)
System Control 3 ($62, color)
7 bit 0 ---- ---- S... ...p | | | +- 1 = Request power off +--------- 0 = WonderSwan Color (SPHINX) 1 = SwanCrystal (SPHINX2)
After setting the "request power off" bit to 1, halting the CPU will cause the console to shut down.
TODO: $AC bit 0 seems to also shut down the console.
System Test ($A3)
Note that this port is only writable as a byte - writing a word to $A2 does not write to this byte.
7 bit 0 ---- ---- .... u?vh | |+- Enable HBlank Timer test | +-- Enable VBlank Timer test +---- Enable UART test
The timer tests ignore the reload value and clock the timers at 3072000? Hz. The enable bit is still respected.
The UART test disables the 9600/38400 baud clock divider, instead operating the EXT port's UART lines at 192000 baud.