Interrupts

Interrupts

The WonderSwan features fourteen different interrupts:

• CPU interrupts - six provided by the V30MZ CPU ($00-$05),
• Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset V):
  • Level - will be constantly requested while enabled and the prerequisite condition is true,
  • Edge - will only be requested while enabled the moment the prerequisite condition becomes true.

Interrupt requests happen when the condition is true and the interrupt is enabled. Note that edge interrupts are only requested once; level interrupts are requested constantly, making acknowledgements ineffective until the condition is cleared or the interrupt is disabled. However, neither disabling an interrupt nor satisfying the condition clears the acknowledgement bit.

The user can additionally make use of all 256 available interrupt vectors in their own code.

List of WonderSwan interrupts

Source	Type	Index	Description
CPU	N/A	$00	DIV or IDIV instruction divide error (division by zero or result overflow)
		$01	Single-step (T flag)
		$02	NMI (non-maskable interrupt)
		$03	INT 3 opcode
		$04	INTO opcode (if V = 1)
		$05	BOUND opcode (if index out of bounds)
Hardware	Level	V + 0	UART Send Ready
	Edge	V + 1	Key Pressed
	Level	V + 2	Cartridge IRQ
		V + 3	UART Receive Ready
	Edge	V + 4	Display Interrupt Line Match
		V + 5	Vertical Blank Timer
		V + 6	Display Vertical Blank
		V + 7	Horizontal Blank Timer

I/O ports

Interrupt Vector Offset ($B0 write)

7  bit  0
---- ----
VVVV V...
|||| |
++++-+---- Interrupt vector offset

Interrupt Vector Request ($B0 read)

7  bit  0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
           from the CPU.

• Bits 7 .. 3 of this will always equal the user-provided vector offset.
• Bits 2 .. 0 of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal 0.

Interrupt Enable ($B2)

7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
           (acts as a mask)

Contrary to other systems, this also controls whether interrupts set the relevant bit in Interrupt Status.

Interrupt Status ($B4 read)

7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- 1 if interrupt requested

Interrupt Acknowledge ($B6 write)

7  bit  0
---- ----
iiii iiii
|||| ||||
++++-++++- Write 1 to clear interrupt request

Interrupt NMI Control ($B7)

7  bit  0
---- ----
...b ....
   |
   +----- Enable NMI on low battery detection