Memory map: Difference between revisions
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The WonderSwan's SoC | The WonderSwan's SoC uses a 20-bit physical memory map, split into three regions with distinct bus widths, timings, and access permissions; | ||
{| class="wikitable" | {| class="wikitable" | ||
|+ WonderSwan | |+ WonderSwan physical memory map | ||
! Bus | ! Bus | ||
! colspan="2" | Address range | ! colspan="2" | Address range | ||
| Line 19: | Line 19: | ||
| style="text-align: center;" | 0x10000<br/>0x1FFFF | | style="text-align: center;" | 0x10000<br/>0x1FFFF | ||
| 8-bit | | 8-bit | ||
| | | 1<sup>(color)</sup>/2 cycles (configurable) | ||
| RW | | RW | ||
|- | |- | ||
| style="text-align: center;" | 0x20000<br/>0xFFFFF | | style="text-align: center;" | 0x20000<br/>0xFFFFF | ||
| 8/16-bit (configurable) | | 8/16-bit (configurable) | ||
| 1/ | | 1/2 cycles (configurable) | ||
| R | | R | ||
|} | |} | ||
| Line 30: | Line 30: | ||
== Internal == | == Internal == | ||
The WonderSwan SoC features an unified memory architecture | The WonderSwan SoC features an unified memory architecture. The CPU, [[Display]] and [[Sound]] components make use of data stored in a shared RAM in distinct segments of the 12.288 MHz SoC clock. This is in contrast to many other platforms which feature, for example, separate video memory. This allows the CPU to modify video and audio data without worrying about wait states or video timing; however, the video and audio components have location and alignment restrictions for data: | ||
This | |||
{| class="wikitable" | {| class="wikitable" | ||
| Line 42: | Line 40: | ||
|- | |- | ||
| style="text-align: center;" | 0x0000 | | style="text-align: center;" | 0x0000 | ||
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x | | colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 4 bytes - far addresses) | ||
|- | |- | ||
| style="text-align: center;" | 0x0400 | | style="text-align: center;" | 0x0400 | ||
| Line 52: | Line 50: | ||
|- | |- | ||
| style="text-align: center;" | 0x4000 | | style="text-align: center;" | 0x4000 | ||
! rowspan="6" style="text-align: center;" | | |||
| style="text-align: center;" | '''Tile data (bank 1)''' | | style="text-align: center;" | '''Tile data (bank 1)''' | ||
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)''' | | rowspan="2" style="text-align: center;" | '''Tile data (bank 0)''' | ||
|- | |- | ||
| style="text-align: center;" | 0x6000 | | style="text-align: center;" | 0x6000 | ||
| rowspan=" | | rowspan="2" style="text-align: center;" | Free RAM | ||
|- | |- | ||
| style="text-align: center;" | 0x8000 | | style="text-align: center;" | 0x8000 | ||
| Line 63: | Line 61: | ||
|- | |- | ||
| style="text-align: center;" | 0xC000 | | style="text-align: center;" | 0xC000 | ||
| style="text-align: center;" | Free RAM | | colspan="2" style="text-align: center;" | Free RAM | ||
|- | |- | ||
| style="text-align: center;" | 0xFE00 | | style="text-align: center;" | 0xFE00 | ||
| Line 95: | Line 93: | ||
| 0x40 (64) bytes | | 0x40 (64) bytes | ||
|} | |} | ||
Note that an element being present on this map does not mean that the space cannot be utilized for other data. For example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space. | |||
== Cartridge == | == Cartridge == | ||
| Line 101: | Line 101: | ||
{| class="wikitable" | {| class="wikitable" | ||
|+ Standard mapper | |+ Standard mapper physical memory map | ||
! Address range | ! Address range | ||
! Bank | ! Bank | ||
Latest revision as of 16:57, 2 August 2024
The WonderSwan's SoC uses a 20-bit physical memory map, split into three regions with distinct bus widths, timings, and access permissions;
| Bus | Address range | Access width | Access speed | Read/Write | |
|---|---|---|---|---|---|
| Internal | 0x00000 0x0FFFF |
16-bit | 1 cycle | RW | |
| Cartridge | 0x10000 0xFFFFF |
0x10000 0x1FFFF |
8-bit | 1(color)/2 cycles (configurable) | RW |
| 0x20000 0xFFFFF |
8/16-bit (configurable) | 1/2 cycles (configurable) | R | ||
Internal
The WonderSwan SoC features an unified memory architecture. The CPU, Display and Sound components make use of data stored in a shared RAM in distinct segments of the 12.288 MHz SoC clock. This is in contrast to many other platforms which feature, for example, separate video memory. This allows the CPU to modify video and audio data without worrying about wait states or video timing; however, the video and audio components have location and alignment restrictions for data:
| Address | WonderSwan | WonderSwan Color (2BPP mode) | WonderSwan Color (4BPP mode) |
|---|---|---|---|
| 0x0000 | Interrupt vectors (256 x 4 bytes - far addresses) | ||
| 0x0400 | Free RAM | ||
| 0x2000 | Tile data (bank 0) | Free RAM | |
| 0x4000 | Tile data (bank 1) | Tile data (bank 0) | |
| 0x6000 | Free RAM | ||
| 0x8000 | Tile data (bank 1) | ||
| 0xC000 | Free RAM | ||
| 0xFE00 | Color palette | ||
| 0xFFFF | |||
In addition, some elements can be placed at configurable locations in RAM, but with restrictions:
| Type | Lowest address | Highest address | Alignment |
|---|---|---|---|
| Screen | 0x0000 | 0x3800 0x7800(color) |
0x800 (2048) bytes |
| Sprite table | 0x0000 | 0x3E00 0x7E00(color) |
0x200 (512) bytes |
| Sound wave table | 0x0000 | 0x3FC0 | 0x40 (64) bytes |
Note that an element being present on this map does not mean that the space cannot be utilized for other data. For example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.
Cartridge
The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a Mapper. There exists a standard layout common to all official mappers:
| Address range | Bank |
|---|---|
| 0x10000 0x1FFFF |
SRAM (or flashable ROM) |
| 0x20000 0x2FFFF |
ROM bank 0 |
| 0x30000 0x3FFFF |
ROM bank 1 |
| 0x40000 0xFFFFF |
ROM linear (EX) bank |
