Interrupts: Difference between revisions
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== Interrupts == | |||
The WonderSwan features fourteen different interrupts: | The WonderSwan features fourteen different interrupts: | ||
| Line 68: | Line 69: | ||
== I/O ports == | == I/O ports == | ||
=== Interrupt Vector === | {{Anchor|Interrupt Vector Offset}} | ||
=== Interrupt Vector Offset ($B0 write) === | |||
<pre> | <pre> | ||
| Line 74: | Line 76: | ||
---- ---- | ---- ---- | ||
VVVV V... | VVVV V... | ||
|||| | | |||
++++-+---- Interrupt vector offset | |||
</pre> | |||
{{Anchor|Interrupt Vector Request}} | |||
=== Interrupt Vector Request ($B0 read) === | |||
<pre> | |||
7 bit 0 | |||
---- ---- | |||
vvvv vvvv | |||
|||| |||| | |||| |||| | ||
++++-++++- Interrupt vector | ++++-++++- Interrupt vector requested | ||
from the CPU. | |||
</pre> | </pre> | ||
=== Interrupt Enable === | * Bits <code>7 .. 3</code> of this will always equal the user-provided vector offset. | ||
* Bits <code>2 .. 0</code> of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal <code>0</code>. | |||
{{Anchor|Interrupt Enable}} | |||
=== Interrupt Enable ($B2) === | |||
<pre> | <pre> | ||
| Line 90: | Line 109: | ||
</pre> | </pre> | ||
=== Interrupt Status === | {{Anchor|Interrupt Status}} | ||
=== Interrupt Status ($B4 read)=== | |||
<pre> | <pre> | ||
| Line 100: | Line 120: | ||
</pre> | </pre> | ||
=== Interrupt Acknowledge === | {{Anchor|Interrupt Acknowledge}} | ||
=== Interrupt Acknowledge ($B6 write)=== | |||
<pre> | <pre> | ||
| Line 110: | Line 131: | ||
</pre> | </pre> | ||
=== Interrupt NMI Control === | {{Anchor|Interrupt NMI Control}} | ||
=== Interrupt NMI Control ($B7)=== | |||
<pre> | <pre> | ||
| Line 116: | Line 138: | ||
---- ---- | ---- ---- | ||
...b .... | ...b .... | ||
| | |||
+----- Enable NMI on low battery detection | +----- Enable NMI on low battery detection | ||
</pre> | </pre> | ||
Revision as of 22:19, 8 February 2024
Interrupts
The WonderSwan features fourteen different interrupts:
- CPU interrupts - six provided by the V30MZ CPU ($00-$05),
- Hardware interrupts - eight provided by the SoC's hardware ($00-$07, or $08-$0F, or $10-$1F, or ... $F8-$FF - controlled by an offset
V):- Level - will be constantly requested while the prerequisite condition is true; interruption can only be prevented by resolving the condition or disabling the interrupt;
- Edge - will only be requested when the prerequisite condition becomes true; acknowledging the interrupt prevents further interruption.
The user can additionally define and use any of the 256 interrupt vectors in their own code.
| Source | Type | Index | Description |
|---|---|---|---|
| CPU | N/A | $00 | DIV or IDIV instruction divide error (division by zero or result overflow) |
| $01 | Single-step (T flag) | ||
| $02 | NMI (non-maskable interrupt) | ||
| $03 | INT 3 opcode | ||
| $04 | INTO opcode (if V = 1) | ||
| $05 | BOUND opcode (if index out of bounds) | ||
| Hardware | Level | V + 0 | UART Send Ready |
| Edge | V + 1 | Key Pressed | |
| Level | V + 2 | Cartridge IRQ | |
| V + 3 | UART Receive Ready | ||
| Edge | V + 4 | Display Interrupt Line Match | |
| V + 5 | Vertical Blank Timer | ||
| V + 6 | Display Vertical Blank | ||
| V + 7 | Horizontal Blank Timer |
I/O ports
Interrupt Vector Offset ($B0 write)
7 bit 0 ---- ---- VVVV V... |||| | ++++-+---- Interrupt vector offset
Interrupt Vector Request ($B0 read)
7 bit 0
---- ----
vvvv vvvv
|||| ||||
++++-++++- Interrupt vector requested
from the CPU.
- Bits
7 .. 3of this will always equal the user-provided vector offset. - Bits
2 .. 0of this will always equal the highest set bit index of Interrupt Status; if all bits in Interrupt Status are clear, they will equal0.
Interrupt Enable ($B2)
7 bit 0
---- ----
iiii iiii
|||| ||||
++++-++++- Hardware interrupt to enable
(acts as a mask)
Interrupt Status ($B4 read)
7 bit 0 ---- ---- iiii iiii |||| |||| ++++-++++- 1 if interrupt requested
Interrupt Acknowledge ($B6 write)
7 bit 0 ---- ---- iiii iiii |||| |||| ++++-++++- Write 1 to clear interrupt request
Interrupt NMI Control ($B7)
7 bit 0 ---- ---- ...b .... | +----- Enable NMI on low battery detection
