SoC: Difference between revisions
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(→System Control 2 ($60, color): document bit 3) |
(hint at $60 bit 0) |
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Line 32: | Line 32: | ||
7 bit 0 | 7 bit 0 | ||
---- ---- | ---- ---- | ||
c4C. i? | c4C. i?sl | ||
||| | | | ||| | || | ||
||| | |+- Cartridge clock speed? | |||
||| | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1 | ||| | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1 | ||
||| +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1 | ||| +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1 |
Revision as of 14:16, 1 September 2023
The WonderSwan SoC is a single-chip solution powering the entirety of the system's hardware - containing the CPU, most peripheral logic, as well as the internal RAM.
There exist three variants of the SoC:
- ASWAN, used in the WonderSwan,
- SPHINX, used in the WonderSwan Color,
- SPHINX2, used in the SwanCrystal.
A fourth variant, CAIRO, was planned[1]. It was designed as an ASWAN with a doubled clock speed and a built-in ADPCM decoder, but was never licensed for a commercial product.
I/O ports
System Control ($A0)
7 bit 0 ---- ---- t??? swcl | |||| | |||+- Boot ROM lockout: 0 = off, 1 = on | ||+-- Color model: 0 = no, 1 = yes | |+--- Cartridge ROM width: 0 = 8-bit, 1 = 16-bit | +---- Cartridge ROM wait state: 0 = +0 cycles, 1 = +2 +--------- MBC authentication successful?
System Control 2 ($60, color)
7 bit 0 ---- ---- c4C. i?sl ||| | || ||| | |+- Cartridge clock speed? ||| | +-- Cartridge SRAM wait state: 0 = +0 cycles, 1 = +1 ||| +---- Cartridge I/O wait state: 0 = +0 cycles, 1 = +1 ||+------- 1 = 4bpp "chunky"; requires all previous |+-------- 1 = 4bpp; requires all previous +--------- 0 = mono, 1 = color; also controls access to WSC-specific features (extra RAM, DMA, etc.)
System Control 3 ($62, color)
7 bit 0 ---- ---- S... ...p | | | +- 1 = Power off system +--------- 0 = WonderSwan Color (SPHINX) 1 = SwanCrystal (SPHINX2)