Memory map: Difference between revisions
(Created page with "The WonderSwan's SoC enforces the following memory map layout: {| class="wikitable" |+ WonderSwan SoC linear memory map ! Bus ! colspan="2" | Address range ! Access width ! Access speed ! Read/Write |- | Internal | colspan="2" style="text-align: center;" | 0x00000<br/>0x0FFFF | 16-bit | 1 cycle | RW |- | rowspan="2" | Cartridge | rowspan="2" style="text-align: center;" | 0x10000<br/>0xFFFFF | style="text-align: center;" | 0x10000<br/>0x1FFFF | 8-bit | ??? | RW |- | styl...") |
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| style="text-align: center;" | 0x10000<br/>0x1FFFF | | style="text-align: center;" | 0x10000<br/>0x1FFFF | ||
| 8-bit | | 8-bit | ||
| | | 1<sup>(color)</sup>/2 cycles (configurable) | ||
| RW | | RW | ||
|- | |- | ||
Line 30: | Line 30: | ||
== Internal == | == Internal == | ||
The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock | The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock. | ||
This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations: | |||
{| class="wikitable" | {| class="wikitable" | ||
Line 52: | Line 52: | ||
|- | |- | ||
| style="text-align: center;" | 0x4000 | | style="text-align: center;" | 0x4000 | ||
! rowspan="6" style="text-align: center;" | | |||
| style="text-align: center;" | '''Tile data (bank 1)''' | | style="text-align: center;" | '''Tile data (bank 1)''' | ||
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)''' | | rowspan="2" style="text-align: center;" | '''Tile data (bank 0)''' | ||
|- | |- | ||
| style="text-align: center;" | 0x6000 | | style="text-align: center;" | 0x6000 | ||
| rowspan=" | | rowspan="2" style="text-align: center;" | Free RAM | ||
|- | |- | ||
| style="text-align: center;" | 0x8000 | | style="text-align: center;" | 0x8000 | ||
Line 63: | Line 63: | ||
|- | |- | ||
| style="text-align: center;" | 0xC000 | | style="text-align: center;" | 0xC000 | ||
| style="text-align: center;" | Free RAM | | colspan="2" style="text-align: center;" | Free RAM | ||
|- | |- | ||
| style="text-align: center;" | 0xFE00 | | style="text-align: center;" | 0xFE00 | ||
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| 0x40 (64) bytes | | 0x40 (64) bytes | ||
|} | |} | ||
Remember that just because an element exists in memory, it doesn't have to be fully utilized; for example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space. | |||
== Cartridge == | == Cartridge == |
Revision as of 17:33, 30 August 2023
The WonderSwan's SoC enforces the following memory map layout:
Bus | Address range | Access width | Access speed | Read/Write | |
---|---|---|---|---|---|
Internal | 0x00000 0x0FFFF |
16-bit | 1 cycle | RW | |
Cartridge | 0x10000 0xFFFFF |
0x10000 0x1FFFF |
8-bit | 1(color)/2 cycles (configurable) | RW |
0x20000 0xFFFFF |
8/16-bit (configurable) | 1/3 cycles (configurable) | R |
Internal
The WonderSwan SoC features an unified memory architecture; that is, the CPU, Display and Sound components can access the RAM in time divisions of the chip's clock.
This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:
Address | WonderSwan | WonderSwan Color (2BPP mode) | WonderSwan Color (4BPP mode) |
---|---|---|---|
0x0000 | Interrupt vectors (256 x 32-bit segment:offset address) | ||
0x0400 | Free RAM | ||
0x2000 | Tile data (bank 0) | Free RAM | |
0x4000 | Tile data (bank 1) | Tile data (bank 0) | |
0x6000 | Free RAM | ||
0x8000 | Tile data (bank 1) | ||
0xC000 | Free RAM | ||
0xFE00 | Color palette | ||
0xFFFF |
In addition, some elements can be placed at configurable locations in RAM, but with restrictions:
Type | Lowest address | Highest address | Alignment |
---|---|---|---|
Screen | 0x0000 | 0x3800 0x7800(color) |
0x800 (2048) bytes |
Sprite table | 0x0000 | 0x3E00 0x7E00(color) |
0x200 (512) bytes |
Sound wave table | 0x0000 | 0x3FC0 | 0x40 (64) bytes |
Remember that just because an element exists in memory, it doesn't have to be fully utilized; for example, it is common for a WonderSwan game to only reserve sixteen out of the 256 interrupt vectors, reusing the remaining 240 as general RAM space.
Cartridge
The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a Mapper. There exists a standard layout common to all official mappers:
Address range | Bank |
---|---|
0x10000 0x1FFFF |
SRAM (or flashable ROM) |
0x20000 0x2FFFF |
ROM bank 0 |
0x30000 0x3FFFF |
ROM bank 1 |
0x40000 0xFFFFF |
ROM linear (EX) bank |