View source for Memory map

The WonderSwan's SoC enforces the following memory map layout:

{| class="wikitable"
|+ WonderSwan SoC linear memory map
! Bus
! colspan="2" | Address range
! Access width
! Access speed
! Read/Write
|-
| Internal
| colspan="2" style="text-align: center;" | 0x00000<br/>0x0FFFF
| 16-bit
| 1 cycle
| RW
|-
| rowspan="2" | Cartridge
| rowspan="2" style="text-align: center;" | 0x10000<br/>0xFFFFF
| style="text-align: center;" | 0x10000<br/>0x1FFFF
| 8-bit
| ???
| RW
|-
| style="text-align: center;" | 0x20000<br/>0xFFFFF
| 8/16-bit (configurable)
| 1/3 cycles (configurable)
| R
|}

== Internal ==

The WonderSwan SoC features an unified memory architecture; that is, the CPU, [[Display]] and [[Sound]] components can access the RAM in time divisions of the chip's clock.

This allows for a mostly CPU-stall-free development experience, but restricts memory layouting. First of all, some elements of the memory live at fixed locations:

{| class="wikitable"
|+ WonderSwan SoC internal memory map
! Address
! WonderSwan
! WonderSwan Color (2BPP mode)
! WonderSwan Color (4BPP mode)
|-
| style="text-align: center;" | 0x0000
| colspan="3" style="text-align: center;" | '''Interrupt vectors''' (256 x 32-bit segment:offset address)
|-
| style="text-align: center;" | 0x0400
| colspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x2000
| colspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x4000
| rowspan="6" style="text-align: center;" |
| style="text-align: center;" | '''Tile data (bank 1)'''
| rowspan="2" style="text-align: center;" | '''Tile data (bank 0)'''
|-
| style="text-align: center;" | 0x6000
| rowspan="3" style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0x8000
| style="text-align: center;" | '''Tile data (bank 1)'''
|-
| style="text-align: center;" | 0xC000
| style="text-align: center;" | Free RAM
|-
| style="text-align: center;" | 0xFE00
| rowspan="2" colspan="2" style="text-align: center;" | '''Color palette'''
|-
| style="text-align: center;" | 0xFFFF
|}

In addition, some elements can be placed at configurable locations in RAM, but with restrictions:

{| class="wikitable"
|+ WonderSwan SoC internal memory layout limitations
! Type
! Lowest address
! Highest address
! Alignment
|-
| Screen
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3800<br/>0x7800<sup>(color)</sup>
| 0x800 (2048) bytes
|-
| Sprite table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3E00<br/>0x7E00<sup>(color)</sup>
| 0x200 (512) bytes
|-
| Sound wave table
| style="text-align: center;" | 0x0000
| style="text-align: center;" | 0x3FC0
| 0x40 (64) bytes
|}

== Cartridge ==

The cartridge part of the memory map is fully controlled by the cartridge bus; this is usually subdivided further by a [[Mapper]]. There exists a standard layout common to all official mappers:

{| class="wikitable"
|+ Standard mapper linear memory map
! Address range
! Bank
|-
| style="text-align: center;" | 0x10000<br/>0x1FFFF
| SRAM (or flashable ROM)
|-
| style="text-align: center;" | 0x20000<br/>0x2FFFF
| ROM bank 0
|-
| style="text-align: center;" | 0x30000<br/>0x3FFFF
| ROM bank 1
|-
| style="text-align: center;" | 0x40000<br/>0xFFFFF
| ROM linear (EX) bank
|}